ISSIE Verilog Component
Contents
Syntax
Both old and new style syntax are supported.
Old style example
module decoder(instr,carry,negative,jump,mux1_sel,mux2_sel);
input [15:0] instr;
input carry,negative;
output jump,mux1_sel,mux2_sel;
wire [3:0] opc = instr[15:12];
assign jump = opc[0] ? c|n : c&n|op[1];
assign mux1_sel = (&op[3:2]);
assign mux2_sel = negative;
endmodule
New style example
module decoder(
input [15:0] instr,
input carry,negative,
output jump,mux1_sel,mux2_sel
);
wire [3:0] opc = instr[15:12];
assign jump = opc[0] ? c|n : c&n|op[1];
assign mux1_sel = (&op[3:2]);
assign mux2_sel = negative;
endmodule
Numbers
Numbers are given in the form: {width}'{radix}{value}
, where radix = 'b
or 'd
or 'h
e.g. 16’h3fa5 , 4’b0101, 16’d154
Operators
Operators perform an opeation on one or more operands within an expression. An expression combines operands with appropriate operators to produce the desired functional expression.
The table shows the operators in descending order of precedence. Operators with equal precedence are shown grouped.
Verilog Operator | Name | Notes and example |
---|---|---|
[ ] | bit-select or part-select | Used to select specific bits of a bus signal. Example: instr[15:8] |
( ) | parenthesis | Used to define the order of operations. Example: (a|b)&c |
! ~ (&) (|) (~&) (~|) |
logical negation negation reduction AND reduction OR reduction NAND reduction NOR |
The Verilog reduction operators are used to convert vectors to scalars. They operate on all of the bits in a vector to convert the answer to a single bit AND Reduction of 4’b1101 is: 0 AND Reduction of 4’b1111 is: 1 OR Reduction of 4’b1101 is: 1 OR Reduction of 4’b0000 is: 0 Example: assign out = (&a); |
{ } | concatenation | example: {a[2:0],b[3:2],2'b01} -> result is 7 bits |
+ - |
binary plus binary minus |
The two operands must be of equal width N The result is also N bits |
« » » |
logical shift left logical shift right arithmetic shift rigth |
The second operand of a shift is an unsigned integer example: assign out[5:0] = in[5:0] << 3; The result has the width of the input |
& | bit-wise AND | The two operands must have the same width |
^ ~^ or ^~ |
bit-wise XOR bit-wise XNOR |
As above |
| | bit-wise OR | As above |
&& | logical AND | logical means that 0->false, anything else -> true Operands can have different width |
|| | logical OR | As above |
? : | conditional | like an if-statement, corresponds to a MUX example: assign jump = opc[0] ? c|n : c&n|op[1]; |