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Digital design that explains itself

ISSIE is a free, cross-platform editor and simulator for digital logic: draw a schematic, simulate it, and see the waveforms — without reading a manual first.

Placing components from the Catalogue onto an ISSIE schematic and wiring them up

Download ISSIE — Windows, macOS and Linux, x64 and Arm64. Unzip and run; no installation, no account.

Follow the one-page tutorial — from an AND gate to a clocked design with waveforms, in one sitting.

See everything it does — the full feature reference.

Why ISSIE exists

Industry CAD systems are powerful and complex to learn. Educational tools are teachable and don't scale. ISSIE is built on the belief that this is a false choice: a tool can be learnable in the first ten minutes and still be used to design and simulate large designs.

It is developed by staff and undergraduates at Imperial College London, and has been used to teach first-year digital electronics since 2020.

Errors tell you how to fix them

This is ISSIE's core design principle, and the clearest thing that sets it apart. Every error names what is wrong, highlights the components and connections responsible on the schematic, and says what to do about it:

What went wrong

What ISSIE tells you

Bus widths disagree

Wrong wire width. Target port expects a 4-bit signal, but source port produces an 8-bit signal.

Two wires into one input

A component input port must have precisely one driving component, but 2 were found. If you want to merge wires together use a MergeWires component, not direct connection.

A .ram file that will not parse

Line 7: 'ff ff ff' has 3 items: valid lines consist of two numbers

Where the fix is unambiguous, ISSIE offers a button that applies it and restarts the simulation, so the loop closes. More on how errors are handled.

No manual needed

Every component in the Catalogue and every field in the Properties pane explains itself when you hover it. The Catalogue's search box matches those explanations as well as the names, so "subtract" finds the N bits XOR. Right-click anything — a component, a wire, the canvas, a sheet in the tree — and you get exactly the actions that apply there, each labelled with its keyboard shortcut. The shortcut table in Info is generated from the table the key dispatcher reads, for your platform, so it cannot list a key that does not work.

Five worked demo projects ship with ISSIE, from a full adder to an EEP1 CPU running a sieve of Eratosthenes. They reset every time you open them, so you can take them apart freely.

Three ways to simulate

The ISSIE waveform simulator showing signals from several sheets of a design

ISSIE has its own simulator. The first version simulated a RISC CPU at 10 cycles per second; it now runs 100,000 cycles of the same CPU in about a second.

Designs that scale

Any sheet can be used as a custom component inside another, any number of times, and the Sheet menu draws the whole project as a tree. Sheets can take integer parametersWIDTH, DEPTH — used in arithmetic expressions for bus widths, constants and memory sizes, with each use of the sheet supplying its own values, so two instances of one sheet can legitimately differ. Ready-made parameterised components can be written as ordinary ISSIE designs and shared as component libraries.

A design can be written out as synthesisable Verilog for your own FPGA toolchain, and a component's logic can be written in SystemVerilog instead of drawn.

Practical matters


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