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Getting Started

Downloading and Running ISSIE

Find the latest ISSIE release. At the bottom of the page, you can find the latest pre-built binary for your platform (Windows or ARM64 Macos). ISSIE will require in total about 200M of disk space.

Creating a New Project

Once you open ISSIE you should see two options: New Project and Open Project.

This process creates a folder where your project will be stored and the first sheet of your project, called main. You can see this by clicking at the Sheets selection button.

Your first design

Let's start with a very simple schematic: a simple 2-input AND gate.

Add the following components to your canvas from the Catalogue tab:

Now make the appropriate wiring to connect all the components by clicking on one port and dragging the wire to the port you want to connect it to.

Connect:

Your design should look like this:

Simulation

Time to simulate the design and see how the output OUT changes as we change the two inputs.

Click the Simulation tab which is located on the top-right corner and then Start Simulation. Now you can change the value of the two inputs and see how the value of the output. Try all 4 combinations of inputs:

and check that the output is correct based on the truth table of the AND gate.

Well Done! You just completed your first ISSIE design.

Exploiting the ISSIE Features

A slightly more complex design

This section will exploit the features of ISSIE to create clean and good-looking schematics when making bigger designs.

Again, simulate the design and check the output remains correct as you change the values of the 4 inputs

Improving the look of a schematic

The schematic here is not easy to read. Let's improve it! The ISSIE canvas is fully customisable to allow the creation of readable and good-looking schematics. Specifically, we can:

  1. Rotate, Flip and Move all symbols
  2. Change name and reposition the symbols' labels relative to the symbols
  3. Manually route any specific segment in a wire
  4. Auto-align elements
  5. Select the desired wire type (radiussed, jump or modern wires)

You can view the shortcuts for all these modifications by clicking on the edit and view menus.

The improved schematic:

Summary

Using Custom Components

The root schematic

In this section we will create a hierarchical design with multiple design sheets by using schematics as custom symbols in other design sheets. Here is the aim: The design we created earlier can be used in a larger design as a decoder of a 4-bit message to produce a true/false result. Therefore, we are going to create a schematic with an asynchronous-read 4-bit ROM using the schematic we created before as a custom symbol.

Steps

  1. Change the name of the current sheet from main to decoder (Sheets -> rename)
  2. Add a new sheet and name it main
  3. Add to the main sheet:
    • Asynchronous ROM (MEMORIES => ROM (asynchronous)). Select 4 bits addressor, 4 bits data and the Enter data later option
    • Your decoder (THIS PROJECT => decoder)
    • 1-bit output named 'RESULT' (INPUT/OUTPUT => Output)
    • 4-bit input named 'Addressor' (INPUT/OUTPUT => Input)
  4. Using 3 SplitWire components (BUSES => SplitWire) separate the 4-bit ROM output to 4 1-bit wires. (see image below)
  5. Make the appropriate connections to achieve the schematic below

Improving the design sheet

It's time to use a hidden part of the ISSIE UI to move ports on custom symbols. ISSIE allows you to re-order and change the side of input and output ports of custom symbols by CTRL + CLICKING ON THE PORT you want to move. The UI, once you realise that you must keep Ctrl (Cmd on Macs) pressed, is intuitive.

Preview how it works in the gif below:

ROM Initialisation

Currently our ROM is empty as we selected the option Enter Data Later before. Let's put some values in our ROM.

  1. Select the ROM and click on the Properties tab
  2. Click on view/edit memory content
  3. Change the content of the 16 memory location available by assigning a random 4-bit number to each one
  4. Click done

ISSIE also allows ROM and RAM initialisation via .ram text files of hex data in the ISSIE directory. See the ISSIE Eratosthenes demo for an example of this. The memory component properties tab offers additional options when there .ram files present.

Simulation

Simulate your design! Change the value of the addressor input and see whether your decoder produces a true or false result for each number you assigned to the ROM.

Waveform Simulation

Creating a clocked design

Let's now modify our previous design to make it clocked (sequential). We use a counter to form a custom addressor that will increment every clock cycle. Using the waveform simulator we will be able to view the output of our circuit for all memory locations. In order to create such designs easily, ISSIE offers a Counter component which, starting from 0, increments by one every clock cycle. Note that counters also have options, under properties, to add Load or Enable inputs.

Add a Counter from the Catalogue (FLIP FLOPS AND REGISTERS). Now select the component and click on Properties. In properties remove the load and enable ports and give them the default functionality (which is what we want in this case): enable=1; load=0;

Edit the previous design to create a schematic like the one below:

Simulating your design

As soon as you connect everything correctly, You can simulate your design. Click on Simulations and then Wave Simulation.

Changing your design

Now, keeping the simulation open, add an extra register between the counter and the ROM address (or make any other change you want) and check that the simulation has the expected output. You can see the changes in the waveform simulator by clicking the Refresh button which will be enabled as soon as there is a change in the schematic.

Truth Table

One of ISSIE's features is the ability to view the truth table for a small combinational circuit.

You can also select your inputs to be algebraic values to get an expression for each of your outputs.

Verilog Component

Last but not least, ISSIE allows you to create combinational custom components by defining the logic in Verilog. Click on Verilog -> New Verilog Component (Catalogue) and write the logic of your decoder in Verilog.

Now what?

You now know how to use ISSIE to create & simulate digital designs.

You can now create your designs (from simple circuits to fully functioning CPUs) and either simulate them or extract them as Verilog to use them with other tools.

For inspiration, look when you start ISSIE under the demos option for Eratosthenes Sieve demo which consists of an EEP1 CPU running an Eratosthenes Sieve program written in EEP1 assembly language. The sieve occupies most of EEP1 RAM and the program takes 200,000 clock cycles to run.

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