ISSIE v5.9.x

For Issie development in 2025 we have:

Feature	Author(s)	Status
Waveform selector	HLP cohort 2025	Finished
Waveform tooltips	TC	Finished
Parameters	HLP cohort 2025	Due to be finished and integrated May
Verilog Compiler	FYP student	Due to be finished June, Integrated July.

Waveform selector

The old waveform selector was very difficult to navigate and confusing. The new selector uses a breadcrumb tree to select sheets and an optimised UI to select component ports. The selector UI was quite difficult to get right. Try it and let us know if it can be improved.

Waveform tooltips

The waveform simulator greys out parts of non-binary waveforms where there is not enough room to print the waveform value. This is the only thing to do, but the loss of information is not nice. Tooltips solve this. Technically these tooltips break normal Issie development rules by using mutable variables and changing the DOM outside of Elmish MVU. The motivation for this is that they must have excellent time and space performance. Poor time performance is less usable, poor space performance impacts how large a design can be simulated. The code is quite short and can be found in the EvilHoverCache module. The mutability is local, so this does not much cause maintenance problems.

This feature finishes the obvious feature set needed for a waveform simulator with a pleasant and intuitive UI. There are as always other advanced features that we could add.

Parameters

Issie has since the beginning had an inherent limitation in that designs cannot be parametrised, e.g. to make register files arbitrary bit-width. This year the HLP class worked on the problem of how to parametrise Issie design sheets. For example, an up/down counter could be designed as a single sheet and then used in a design multiple times as counters of different widths.

The problem is complex because a full solution has parameters can be defined using parameter expressions of other parameters. This means that a design can no longer be explored as a set of independent design sheets. The actual widths in a design sheet can have different values for different instances of the sheet in the design. Correctness of parameter values then becomes more difficult to explain with Issie-quality error messages.

Verilog Compiler

We have an FYP student looking at how to extend the current Verilog editor and compiler. Our ambition is that Issie should be able to compile nearly all synthesisable Verilog that represents purely synchronous designs into Issie design sheets. These can then be simulated using Issie, and viewed as schematics. That will allow Issie to be used seamlessly to support HDL learning, and also make Issie more useful for research or commercial medium-scale design and test.

The vision is that eventually we make both of the transformations:

• Issie schematics -> Verilog output
• Verilog input -> Issie schematics

Complete and nicely human readable so that an Issie schematic generated from Verilog, or Verilog output from a schematic, makes it easy for a novice to understand Verilog hardware.