ISSIE v3.0.0

One year on and Issie has survived another year of intensive testing by EEE students with, this time, no significant bugs!

This Summer we have some significant upgrades, described below. With these, Issie is now up to 24K lines of F#!

New Schematic Editor: v3.0.0

The initial schematic editor could only autoroute from right edge outputs to left edge inputs. That was quite limiting and we were finding that with no ability to rotate or flip components designs were often badly routed. We partly fixed this by allowing custom component (subsheet instance) ports to be arbitrarily positioned but the UI for this was unpleasant and required chnaging component poistions on the underlying sheet.

So this year the HLP students were set the task of improving the schemetic editor, allowing arbitrary auto-routing, component rotating and flipping, MUXes with select inputs on a different edge from outputs and inputs. As is often the case they exceeded this brief and in v3.0.0 we have their work put together and tidied up, with very many enhancements over v2.

Polishing: v3.0.0

Little things for usability, like recent project lists and a persistent load/save directory, have been implemented for greater usability, and all minor bugs except for waveform simulator top-level UI weirdness have been closed. The waveform simulator is currently being overhauled, hence its top-level UI will be part of that.

Waveform Simulator

The code here is very complex and difficult to work with. It is being re-implemented with the idea that we can make it more interactive and add functionality. Since this is a student's project work the end result is still not clear! Expect results released in early July.

Step Simulator

The step simulator is being reworked with some added feaures (another student project). Again exact functionality is still under consideration: expect results released in early July.

Looking forward

Over the Summer we hope for two major improvements:

• Verilog components. We will implement a verilog (subset) parser and allow at least combinational Verilog blocks as components.
• Parametrised sheets. Library components in Issie are currently limited by the lack of sheet-level parameters (for example bus width). We would like to implement this so that complex components can be implemented as libraries.

Have a look at the issues and associated discussions for where we are on these two projects - contribute if you are interested or have strong requirements.