ISSIE v3.0.9 - Happy Christmas!

Happy Christmas and New Year to all Issie users!

The major changes from last year have now survived Autumn Term testing with a few minor changes and fixes to improve the all-new waveform simulation display. Next term will have more serious user testing with a few hundred students using the waveform simulator to run and debug a multi-sheet EEP1 CPU.

For the period of the Spring term there will be no new features - and bug fixes as needed. We hope not many will be needed.

This year the main Issie improvement will be the simulator, where 0x6770 (Yujie Wang) is working on a branch that will use a variety of techniques to speed up simulation by a large amount. Yujie will also be making a few additions to the recommended Issie tool chain and style guide.

In addition a major extension is expected to the current simple Verilog component feature. Petra Ratkai petraratkai is working on a much more complete Verilog compiler that will move Issie more towards non-schematic use. The hope is that eventually for advanced work schematics can be used for structural code an top-level hierarchy, and RTL modules implemented in HDL.

Tom Clarke, December 2022