Verilog output

ISSIE can output any design as synthesisable or simulatable Verilog HDL. Every ISSIE design sheet is turned into a single Verilog module. The Verilog output Sheet menu item leads to a dialog screen:

The buttons provide help on how to generate and use output with Verilog simulation or the Issie-stick FPGA hardware.

Verilog output is not currently used much: but the code to generate it is very simple and easily changed. Please add issues if what currently exists does not fit your requirements.