ISSIE v3.0.1

The Summer has been highly productive for Issie, with work from Jason, Aditya, and Archontis - whose time working on a 6 month placement has been invaluable. I am very grateful for their help.

We have added another 11K lines of code to Issie. This comprises many new features, but also a lot of work to fix bugs and reduce technical debt. Part of this is what you might call user interface technical debt. As new features are added some of the initial UI design elements no longer work intuitively and so they must be reworked. This was true for the waveform simulation. We now have a redesigned user interface where step simulation and waveform simulation work the same way and enhance each other. In addition the waveform Viewer now works without limitations on very large designs and allows design correction and resimulation without losing the simulation context. This should significantly speed up edit/debug cycles on larger designs.

Two other notable developments implemented by Archontis.

1. We have an initial Verilog entry window to allow complex combinational logic to be written as equations. Although the current impelmentation is a subset of VHDL it has two merits: the user in-editor error messages are instant and very understandable, and the parsing logic is implemented using a Nearley Parser. Nearley grammars are powerful and easy to write, they also make it easy to get detailed and precise error messages from the parse - that is needed for a user-friendly Verilog entry system! Expanding Verilog input to the full language will be a future project, this is a secure foundation.
2. We have completed the interface to Issie stick hardware so that designs can be run on FPGAs and debugged (with Issie as debugger).

For me the most interesting take home has been the ease with which even a fairly large design (now 36K lines of F# in 60 files) can be reworked. This is a merit of the "near functional" architecture using F# and Elmish MVU. Problems with technical debt have come from original code that breaks the Issie guidelines, or where requirements have changed so much that significant redesign is needed.

Technically, most interesting was integrating a Javascript Nearley parser, and adding Optics to make the syntax for nested state changes more readable. For users, we have a lot of little features and UI improvements too numerous to mention here that fill gaps in Issie making it a better CAD tool while keeping its extreme simplicity.

We are reasonably confident that the changes will make an even better experience for the new EEE 1st year DECA students!

Looking forward: the two major improvements now wanted are a faster simulator more capable in big designs, and a complete Verilog language implementation.

Tom Clarke, September 2022