What is ISSIE?

Interactive Schematic Simulator with Integrated Editor (ISSIE) is a very easy to use desktop application which supports digital circuit design and simulation. It is targeted at both novice University and professional users who want to implement and test high productivity hierarchical digital circuit design. Issie is designed to be beginner-friendly and guide the users toward their goals via clear UI signposting, error messages that explain how to correct the error, and visual clues. A design aim is to make Issie scalable. It is intuitive to use with small single-sheet circuits and also highly productive debugging complex CPU designs made from 50 sheets and hundreds of thousands of components. The motivation for Issie was the observation that during digital lab work in EEE, previously, more time was spent learning to use (or cope with subtle bugs in) large commercial hardware design tools, than was spent learning digital design. We wanted a tool as powerful as those commercial packages which was more productive.

• Issie is developed as an open source project mostly by 3rd and 4th year EEE students at Imperial College London
• Issie has been well tested on hierarchical designs with up to 15,000 schematic components. We expect it to be performant on much larger designs as well. The simulation speed is approximately 50,000 component-clocks per ms (on an 11th gen Intel laptop). Thus a circuit with 1000 components would run at 50,000 clocks per second. Issie creates fully synchronous circuits with a single clock: logic with asynchronous loops is currently not supported (a feature, since 95% of the time asynchronous circuits cause trouble) although this is on the roadmap for possible implementation in 2023-4.
• Issie designs can be exported to Verilog and synthesised on FPGAs with a simple workflow.
• User-friendly design entry using a restricted subset of Verilog is supported as an alternative to implementing combinational logic using gates. It is a lot of work implementing a full verilog compiler with Issie's user-frindly error messages, currently the Verilog support is incomplete. We have better Verilog support on the roadmap.
• The application comprises about 42K lines of F#, a functional programming language taught by the EEE department in the module High Level Programming, which gets transpiled to JavaScript via the Fable compiler and the Elmish web framework. Electron is then used to convert the developed web-app to a cross-platform application.
• Issie is in active use teaching a cohort of 200 1st year students at Imperial College in the EEE department's Digital Electronics and Computer Architecture module.
• Many 1st year students enjoy using Issie so much that they are inspired to learn F# and help developing Issie in the Summer vacation!

Key Features

• Hierarcical Design with Schematic Components

  ISSIE has an extensive library of schematic components available in the 'Catalogue' menu. Components include low-level gates, flipflops, and multiplexers, as well as larger blocks: RAMs, ROMs, configurable n-bit registers, counters and adders. Viewer components are used to (optionally) view simulation waveforms of nodes on sub-sheets. Wire label components allow any number of nodes on one design sheet to be connected without visible wires. More complex functions can quickly be constructed as sub-sheets and then used as a 'custom component' (found under 'THIS PROJECT'). Custom components can have shape and I/O positions altered at any time via an intuitive and fast drag and drop GUI

• Wire Routing

  ISSIE schematic component ports are connected using drag-and-drop: each connection represents a wire or bus. ISSIE has two methods of routing wires: auto-routing and manual-routing.
  
  Wires will all start out as auto-routed, which means that the wire’s path is created automatically by the program. This path will update when moving any connected components. ISSIE also allows for manual routing, where the user may manipulate segments of the wire as desired to make the circuit more readable. Much care has been put into a user interface for routing which just works quickly with no learning curve.

• Canvas Customization

  The ISSIE canvas is fully customisable to allow the creation of readable and good-looking schematics. Specifically:
  
  (a) Rotate, flip and Move all symbols
  (b) Change and move around the symbols' labels
  (c) Manually route wires as you like
  (d) Auto-align elements
  (e) Select the wire type you desire (radiussed, jump or modern wires)

• Verilog Component

  ISSIE allows users to create combinational components by defining their logic in Verilog. Such component can be used as a Custom Component in all designs.
  
  For more information see the Verilog Component page

• Step Simulation

  Step Simulation allows the user to 'step' or cycle through each clock tick, and view the current design sheet's Output and Viewer component information. It also allows users to view how the state changes in stateful components such as RAM.

• Waveform Simulation

  Waveform Simulation allows the user to see the values in each selected set of connected wires (net) over time as a waveform. The waveform simulator uses a drag-and-drop GUI to delete or reorder waveforms, and a separate project explorer window to add them. Hovering on a waveform name highlights its component and all connected busses on its design sheet. Any design sheet may be viewed or edited and the simulation refreshed to see changes immediately. The values in the waveform simulator can be viewed in various formats: binary, hexadecimal, unsigned decimal and signed decimal. The Waveform Simulator uses a draggable sidebar to partition screen space dynamically between waveforms and circuit.
  
  Waveform Simulation also allows for the simulation and contents viewing of memory components such as RAM.

• Truth Table

  ISSIE allows users to view the truth table for a selected circuit of combinational logic. This can be either the full truth table or a reduced one by denoting all Don't Cares with 'X's.
  
  Furthermore, users can set any number of inputs as algebra. The resultant truth table will show outputs as a function of the inputs.

• Verilog Output

  Users may convert their ISSIE schematic design into a Verilog file using the "Write design as Verilog" option found in the header bar of the application. This allows great flexibility as ISSIE designs may be used in more complex design tools and other programs that use Verilog; allowing ISSIE to be used as a top-level design that can be further developed if needed. Verilog output for simulation or synthesis is documented as part of the Verilog write process, this includes links to a YoSys workflow for synthesis on FPGAs. Imperial College users can download a pre-installed VM for this workflow, the VHDL output is standalone and should work with other synthesis methods

• Memory Editor

  ISSIE allows users to directly edit the contents of Memory components, for more versatility and ease of use. Memory contents can also be exported and imported via .ram files

Running Issie

The download button on this page take you to the Issie latest release page. Scroll down the top release on this page till you get the the Assets section - this has binaries for windows and macos PCs. Download the appropriate one and unzip it anywhere. No installation is required - Issie runs from the unzipped files under windows if you double-click the top-level Issie.exe file with the blue Issie chip icon. For more information see Getting Started or read the User Guide.

Acknowledgements

• Marco Selvatici for the 8K lines of base code written for his 3rd year BEng FYP
• Edoardo Santi for work improving Issie over Summer 2020 and creating the waveform simulator
• High Level Programming 2020/21 cohort for providing the base code of the new schematic editor
• Jo Merrick for work improving ISSIE for her 3rd year BEng FYP
• High Level Programming 2021/22 cohort for implementing a much enhanced schematic editor
• All 2020/2021 1st year undergraduate students of the EEE department, Imperial College London, for acting as excellent and unpaid beta-testers in their DECA module!
• Jason Zheng for improving the waveform simulator for his 4th year MEng FYP
• Aditya Deshpande for creating the truth table for his 4th year MEng FYP
• Archontis Pantelopoulos for creating the Verilog Component and improving ISSIE over Summer 2022
• Petra Ratkai and Yujie Wang for imporving the Verilog compiler & Issie simulator in 2022-23.
• Dr Tom Clarke for running HLP and his continued work maintaining and improving ISSIE throughout
  
  

Contact

If you encounter any problems using or downloading the software, please see the Gihub Issue page, or create a new issue on the ISSIE GitHub repository. Any feedback and suggestions are also welcome!