ErrorCheck (issie)

ErrorCheck Module

Namespace: global
Assembly: Renderer.dll

Functions and values

Function or value	Description
`checkAllOutputsAssigned ast portMap portSizeMap paramMap linesLocations errorList` Full Usage: `checkAllOutputsAssigned ast portMap portSizeMap paramMap linesLocations errorList` Parameters: ast : `VerilogInput` portMap : `Map<string, DeclarationDU>` portSizeMap : `Map<string, int>` paramMap : `Map<string, int>` linesLocations : `int list` errorList : `ErrorInfo list` Returns: `ErrorInfo list`	Checks if all declared output ports have a value assigned to them The check is done bit-by-bit ast : `VerilogInput` portMap : `Map<string, DeclarationDU>` portSizeMap : `Map<string, int>` paramMap : `Map<string, int>` linesLocations : `int list` errorList : `ErrorInfo list` Returns: `ErrorInfo list`
`checkAssignmentWidths ast linesLocations portSizeMap wireSizeMap arraySizeMap paramMap errorList` Full Usage: `checkAssignmentWidths ast linesLocations portSizeMap wireSizeMap arraySizeMap paramMap errorList` Parameters: ast : `VerilogInput` linesLocations : `int list` portSizeMap : `Map<string, int>` wireSizeMap : `Map<string, int>` arraySizeMap : `Map<string, (int * int array)>` paramMap : `Map<string, int>` errorList : `ErrorInfo list` Returns: `ErrorInfo list`	Checks if the RHS expression is wider than the LHS of an assignment. Checks every assignment: continuous and combinational ast : `VerilogInput` linesLocations : `int list` portSizeMap : `Map<string, int>` wireSizeMap : `Map<string, int>` arraySizeMap : `Map<string, (int * int array)>` paramMap : `Map<string, int>` errorList : `ErrorInfo list` Returns: `ErrorInfo list`
`checkForLoopUnrollCost ast paramMap linesLocations errorList` Full Usage: `checkForLoopUnrollCost ast paramMap linesLocations errorList` Parameters: ast : `VerilogInput` paramMap : `Map<string, int>` linesLocations : `int list` errorList : `ErrorInfo list` Returns: `ErrorInfo list`	Checks estimated program size after loop unrolling. ast : `VerilogInput` paramMap : `Map<string, int>` linesLocations : `int list` errorList : `ErrorInfo list` Returns: `ErrorInfo list`
`checkForLoopVar ast linesLocations errorList` Full Usage: `checkForLoopVar ast linesLocations errorList` Parameters: ast : `VerilogInput` linesLocations : `int list` errorList : `ErrorInfo list` Returns: `ErrorInfo list`	Checks that loop variables in for loops are not assigned to inside the loop body ast : `VerilogInput` linesLocations : `int list` errorList : `ErrorInfo list` Returns: `ErrorInfo list`
`checkIODeclarations ast portWidthDeclarationMap portLocationMap linesLocations nonUniquePortDeclarations portMap project errorList` Full Usage: `checkIODeclarations ast portWidthDeclarationMap portLocationMap linesLocations nonUniquePortDeclarations portMap project errorList` Parameters: ast : `VerilogInput` portWidthDeclarationMap : `Map<string, (int * int)>` portLocationMap : `Map<string, int>` linesLocations : `int list` nonUniquePortDeclarations : `string list` portMap : `Map<string, DeclarationDU>` project : `Project` errorList : `ErrorInfo list` Returns: `ErrorInfo list`	Checks whether all ports defined as input/output are declared as ports in the module header Also checks for double definitions and for input ports not used in the assignments ast : `VerilogInput` portWidthDeclarationMap : `Map<string, (int * int)>` portLocationMap : `Map<string, int>` linesLocations : `int list` nonUniquePortDeclarations : `string list` portMap : `Map<string, DeclarationDU>` project : `Project` errorList : `ErrorInfo list` Returns: `ErrorInfo list`
`checkIOWidthDeclarations ast paramMap linesLocations errorList` Full Usage: `checkIOWidthDeclarations ast paramMap linesLocations errorList` Parameters: ast : `VerilogInput` paramMap : `Map<string, int>` linesLocations : `int list` errorList : `ErrorInfo list` Returns: `ErrorInfo list`	Checks whether the IO declarations have correct width format (i.e. Little-endian) ast : `VerilogInput` paramMap : `Map<string, int>` linesLocations : `int list` errorList : `ErrorInfo list` Returns: `ErrorInfo list`
`checkInputsAssigned ast linesLocations portMap errorInfoList` Full Usage: `checkInputsAssigned ast linesLocations portMap errorInfoList` Parameters: ast : `VerilogInput` linesLocations : `int list` portMap : `Map<string, DeclarationDU>` errorInfoList : `ErrorInfo list` Returns: `ErrorInfo list`	ast : `VerilogInput` linesLocations : `int list` portMap : `Map<string, DeclarationDU>` errorInfoList : `ErrorInfo list` Returns: `ErrorInfo list`
`checkParamsUsed ast linesLocations paramMap errorList` Full Usage: `checkParamsUsed ast linesLocations paramMap errorList` Parameters: ast : `VerilogInput` linesLocations : `int list` paramMap : `Map<string, int>` errorList : `ErrorInfo list` Returns: `ErrorInfo list`	Checks parameters declared have been used ast : `VerilogInput` linesLocations : `int list` paramMap : `Map<string, int>` errorList : `ErrorInfo list` Returns: `ErrorInfo list`
`checkUnsupportedKeywords ast linesLocations errorList` Full Usage: `checkUnsupportedKeywords ast linesLocations errorList` Parameters: ast : `VerilogInput` linesLocations : `int list` errorList : `ErrorInfo list` Returns: `ErrorInfo list`	ast : `VerilogInput` linesLocations : `int list` errorList : `ErrorInfo list` Returns: `ErrorInfo list`
`checkWiresAndAssignments ast portMap portSizeMap portWidthDeclarationMap inputNameList linesLocations wireNameList wireSizeMap wireLocationMap arraySizeMap paramMap errorList` Full Usage: `checkWiresAndAssignments ast portMap portSizeMap portWidthDeclarationMap inputNameList linesLocations wireNameList wireSizeMap wireLocationMap arraySizeMap paramMap errorList` Parameters: ast : `VerilogInput` portMap : `Map<string, DeclarationDU>` portSizeMap : `Map<string, int>` portWidthDeclarationMap : `Map<string, (int * int)>` inputNameList : `string list` linesLocations : `int list` wireNameList : `string list` wireSizeMap : `Map<string, int>` wireLocationMap : `Map<string, int>` arraySizeMap : `Map<string, (int * int array)>` paramMap : `Map<string, int>` errorList : `ErrorInfo list` Returns: `ErrorInfo list`	Checks one-by-one all wire and output port assignments for: 1) LHS Name and Width 2) RHS Names 3) RHS Width of inputs/wires 4) Width LHS = Width RHS ast : `VerilogInput` portMap : `Map<string, DeclarationDU>` portSizeMap : `Map<string, int>` portWidthDeclarationMap : `Map<string, (int * int)>` inputNameList : `string list` linesLocations : `int list` wireNameList : `string list` wireSizeMap : `Map<string, int>` wireLocationMap : `Map<string, int>` arraySizeMap : `Map<string, (int * int array)>` paramMap : `Map<string, int>` errorList : `ErrorInfo list` Returns: `ErrorInfo list`
`createErrorMessage newLinesLocations currLocation message extraMessages name` Full Usage: `createErrorMessage newLinesLocations currLocation message extraMessages name` Parameters: newLinesLocations : `int list` currLocation : `int` message : `string` extraMessages : `ExtraErrorInfo array` name : `string` Returns: `ErrorInfo list`	Helper function to create an ErrorInfo-type Error Message given the location, the variable name, and the message newLinesLocations : `int list` currLocation : `int` message : `string` extraMessages : `ExtraErrorInfo array` name : `string` Returns: `ErrorInfo list`
`getArraySizeMap items paramMap` Full Usage: `getArraySizeMap items paramMap` Parameters: items : `ItemDU list` paramMap : `Map<string, int>` Returns: `Map<string, (int * int array)>`	items : `ItemDU list` paramMap : `Map<string, int>` Returns: `Map<string, (int * int array)>`
`getExtraParamErrors ast wireSizeMap portSizeMap linesLocations origin project modInst comp` Full Usage: `getExtraParamErrors ast wireSizeMap portSizeMap linesLocations origin project modInst comp` Parameters: ast : `VerilogInput` wireSizeMap : `Map<string, int>` portSizeMap : `Map<string, int>` linesLocations : `int list` origin : `CodeEditorOpen` project : `Project` modInst : `ModuleInstantiation` comp : `LoadedComponent` Returns: `ErrorInfo list`	ast : `VerilogInput` wireSizeMap : `Map<string, int>` portSizeMap : `Map<string, int>` linesLocations : `int list` origin : `CodeEditorOpen` project : `Project` modInst : `ModuleInstantiation` comp : `LoadedComponent` Returns: `ErrorInfo list`
`getIdentifiers identifiers node` Full Usage: `getIdentifiers identifiers node` Parameters: identifiers : `string list` node : `ASTNode` Returns: `string list`	identifiers : `string list` node : `ASTNode` Returns: `string list`
`getInputNames portMap` Full Usage: `getInputNames portMap` Parameters: portMap : `Map<'a, DeclarationDU>` Returns: `'a list`	Returns the names of the ports declared as INPUT portMap : `Map<'a, DeclarationDU>` Returns: `'a list`
`getInputSizeMap inputNameList portSizeMap` Full Usage: `getInputSizeMap inputNameList portSizeMap` Parameters: inputNameList : `'a list` portSizeMap : `Map<'a, 'b>` Returns: `Map<'a, 'b>`	inputNameList : `'a list` portSizeMap : `Map<'a, 'b>` Returns: `Map<'a, 'b>`
`getNotUniquePortDeclarations items` Full Usage: `getNotUniquePortDeclarations items` Parameters: items : `ItemDU list` Returns: `string list`	items : `ItemDU list` Returns: `string list`
`getParamDeclarations paramDeclarations node` Full Usage: `getParamDeclarations paramDeclarations node` Parameters: paramDeclarations : `Parameter list` node : `ASTNode` Returns: `Parameter list`	paramDeclarations : `Parameter list` node : `ASTNode` Returns: `Parameter list`
`getParamMap ast linesLocations items` Full Usage: `getParamMap ast linesLocations items` Parameters: ast : `VerilogInput` linesLocations : `int list` items : `ItemDU list` Returns: `Map<string, int> * ErrorInfo list`	ast : `VerilogInput` linesLocations : `int list` items : `ItemDU list` Returns: `Map<string, int> * ErrorInfo list`
`getParamsUsed ast paramMap` Full Usage: `getParamsUsed ast paramMap` Parameters: ast : `VerilogInput` paramMap : `Map<string, int>` Returns: `List<string>`	ast : `VerilogInput` paramMap : `Map<string, int>` Returns: `List<string>`
`getPortMap items` Full Usage: `getPortMap items` Parameters: items : `ItemDU list` Returns: `Map<string, DeclarationDU>`	Returns the port-type map (e.g. (port "a" => INPUT)) items : `ItemDU list` Returns: `Map<string, DeclarationDU>`
`getPortSizeAndLocationMap items paramMap` Full Usage: `getPortSizeAndLocationMap items paramMap` Parameters: items : `ItemDU list` paramMap : `Map<string, int>` Returns: `Map<string, int> * Map<string, int>`	Returns the port-size map (e.g. (port "a" => 4 bits wide)) items : `ItemDU list` paramMap : `Map<string, int>` Returns: `Map<string, int> * Map<string, int>`
`getPortWidthDeclarationMap items paramMap` Full Usage: `getPortWidthDeclarationMap items paramMap` Parameters: items : `ItemDU list` paramMap : `Map<string, int>` Returns: `Map<string, (int * int)>`	Returns the port-width declaration map (e.g. ( port "a" => (4,0) )) items : `ItemDU list` paramMap : `Map<string, int>` Returns: `Map<string, (int * int)>`
`getSemanticErrors ast linesLocations origin project` Full Usage: `getSemanticErrors ast linesLocations origin project` Parameters: ast : `VerilogInput` linesLocations : `int list` origin : `CodeEditorOpen` project : `Project` Returns: `ErrorInfo list`	ast : `VerilogInput` linesLocations : `int list` origin : `CodeEditorOpen` project : `Project` Returns: `ErrorInfo list`
`getSemanticErrorsNoParamOverride ast linesLocations paramMap origin project` Full Usage: `getSemanticErrorsNoParamOverride ast linesLocations paramMap origin project` Parameters: ast : `VerilogInput` linesLocations : `int list` paramMap : `Map<string, int>` origin : `CodeEditorOpen` project : `Project` Returns: `ErrorInfo list`	Helper error-finder function Called again in module instantations after parameters are evaluated to ensure overriding works Returns a list of errors (type ErrorInfo) ast : `VerilogInput` linesLocations : `int list` paramMap : `Map<string, int>` origin : `CodeEditorOpen` project : `Project` Returns: `ErrorInfo list`
`getWireLocationMap items` Full Usage: `getWireLocationMap items` Parameters: items : `ItemDU list` Returns: `Map<string, int>`	items : `ItemDU list` Returns: `Map<string, int>`
`getWireNames items` Full Usage: `getWireNames items` Parameters: items : `ItemDU list` Returns: `string list`	items : `ItemDU list` Returns: `string list`
`nameCheck ast linesLocations origin project errorList` Full Usage: `nameCheck ast linesLocations origin project errorList` Parameters: ast : `VerilogInput` linesLocations : `int list` origin : `CodeEditorOpen` project : `Project` errorList : `ErrorInfo list` Returns: `ErrorInfo list`	Checks if the name of the module is valid (i.e. this sheet doesn't exist) ast : `VerilogInput` linesLocations : `int list` origin : `CodeEditorOpen` project : `Project` errorList : `ErrorInfo list` Returns: `ErrorInfo list`
`portCheck ast linesLocations errorList` Full Usage: `portCheck ast linesLocations errorList` Parameters: ast : `VerilogInput` linesLocations : `int list` errorList : `ErrorInfo list` Returns: `ErrorInfo list`	Checks whether all ports given in the beginning of the module are defined as input/output Also if all ports have distinct names ast : `VerilogInput` linesLocations : `int list` errorList : `ErrorInfo list` Returns: `ErrorInfo list`
`unaryTreeToString treeDepth targetLength unary` Full Usage: `unaryTreeToString treeDepth targetLength unary` Parameters: treeDepth : `int` targetLength : `int` unary : `OneUnary` Returns: `string`	Helper recursive function to transform the produced OneUnary-type tree by RHSUnaryAnalysis to a string which can be used for ErrorInfo treeDepth : `int` targetLength : `int` unary : `OneUnary` Returns: `string`