RamStore Module
How a read/write memory's contents are held while a simulation runs. See [docs/dev/ramRepresentation.md] for why this exists and what it is worth. In short: the contents used to be a `Map` and a fresh snapshot of it was stored for every clock step, so a write cost an AVL path copy plus two boxed `BigInt`s, a read cost a descent with boxed comparisons, and a long waveform simulation retained every version it had ever made. Here - a read during simulation is an array index, - a write appends two numbers to shared flat arrays, - the value an address held at any past step is a binary search of that address's own writes, whose cost does not depend on how far the cursor moved, and - nothing at all is allocated per step. **Storage is CSR.** Every address that is ever written is given a *slot* number, and a slot's writes are one contiguous run of the shared `IStep`/`IVal` arrays, delimited by `Start`. The alternative - a growable list per address - costs a record and two list objects per address, which is around 230 bytes for what may be a single 8-byte write. That is affordable for one big RAM and is not for a hundred small ones, which between them have just as many addresses. Recent writes go to a small tail and are folded in by `compact`. **Where this file sits.** F# compile order is the dependency layering, and `SimGraphTypes.SimulationComponentState` names this type, so it has to be compiled before `SimGraphTypes.fs` and cannot live in the `FastSim` block with the rest of the simulator. It depends on nothing but `CommonTypes`, which is what makes that possible. **Mutability.** This is the same layer as the step arrays, which are already mutable, and [docs/mutableState.md] allows it for a measured performance reason - the whole point here is to stop allocating. Nothing mutable escapes: `Memory1` remains the immutable type everywhere outside the running simulation, and `toMemory` builds one on demand.
Types and nested modules
Functions and values
| Function or value | Description |
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Full Usage:
liveCountExceeds ram step limit
Parameters:
Ram
step : int
limit : int
Returns: bool
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Whether more than `limit` words were non-zero at the end of `step`. This is all the RAM table needs: it chooses between listing every non-zero location and a windowed display, and the exact figure never appears. Asking the cheaper question means the walk stops as soon as the answer is settled, and usually it never starts - a memory that has never had more than `limit` addresses written cannot have more than `limit` non-zero.
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Current contents at `addr`, on the bigint-value path. A store keeps values in one of two forms, chosen once by word width, and the caller has to ask for the one it holds - the evaluators do, via `BigIntState`. Asking for the other would otherwise read an array that was never filled, so it is redirected rather than trusted.
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Full Usage:
writeAddrBigIntDataBigInt ram step addr value
Parameters:
Ram
step : int
addr : bigint
value : bigint
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Full Usage:
writeAddrBigIntDataUInt32 ram step addr value
Parameters:
Ram
step : int
addr : bigint
value : uint32
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Full Usage:
writeAddrUInt32DataBigInt ram step addr value
Parameters:
Ram
step : int
addr : uint32
value : bigint
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Full Usage:
writeAddrUInt32DataUInt32 ram step addr value
Parameters:
Ram
step : int
addr : uint32
value : uint32
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Full Usage:
writeBigVal ram step addr value
Parameters:
Ram
step : int
addr : uint32
value : bigint
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Full Usage:
writeU ram step addr value
Parameters:
Ram
step : int
addr : uint32
value : uint32
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Record a write, unless it changes nothing. A write of the value already at that address is not a write: skipping it costs one comparison on a value the reducer has already read (it is the old contents, which a RAM returns as its output) and saves an entry, which every later search and every later compaction then does not have to walk. Nothing observable changes - the contents are identical by definition, and the RAM table's read/write highlighting comes from the input step arrays rather than from here.
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