ErrorCheckProcedural (issie) | issie

ErrorCheckProcedural Module

Namespace: global
Assembly: Renderer.dll

Types

Type	Description
Graph

Functions and values

Function or value	Description
`allCasesCovered caseStmt portSizeMap wireSizeMap` Full Usage: `allCasesCovered caseStmt portSizeMap wireSizeMap` Parameters: caseStmt : `CaseStatementT` portSizeMap : `Map<string, int>` wireSizeMap : `Map<string, int>` Returns: `bool`	Used for checking if a variable is assigned in every branch, see checkVariablesAlwaysAssigned caseStmt : `CaseStatementT` portSizeMap : `Map<string, int>` wireSizeMap : `Map<string, int>` Returns: `bool`
`checkAlwaysCombRHS ast linesLocations portSizeMap wireSizeMap errorList` Full Usage: `checkAlwaysCombRHS ast linesLocations portSizeMap wireSizeMap errorList` Parameters: ast : `VerilogInput` linesLocations : `int list` portSizeMap : `Map<string, int>` wireSizeMap : `Map<string, int>` errorList : `ErrorInfo list` Returns: `ErrorInfo list`	check that if an always block writes to and reads from the same variable, variable is assigned first and written later a=1; b=a; a=0; -> this shouldn't be allowed ast : `VerilogInput` linesLocations : `int list` portSizeMap : `Map<string, int>` wireSizeMap : `Map<string, int>` errorList : `ErrorInfo list` Returns: `ErrorInfo list`
`checkCasesStatements ast linesLocations portSizeMap wireSizeMap errorList` Full Usage: `checkCasesStatements ast linesLocations portSizeMap wireSizeMap errorList` Parameters: ast : `VerilogInput` linesLocations : `int list` portSizeMap : `Map<string, int>` wireSizeMap : `Map<string, int>` errorList : `ErrorInfo list` Returns: `ErrorInfo list`	Checks the case items of the case statements: - Repeated cases - Wrong width ast : `VerilogInput` linesLocations : `int list` portSizeMap : `Map<string, int>` wireSizeMap : `Map<string, int>` errorList : `ErrorInfo list` Returns: `ErrorInfo list`
`checkClk ast linesLocations portMap errorList` Full Usage: `checkClk ast linesLocations portMap errorList` Parameters: ast : `VerilogInput` linesLocations : `int list` portMap : `Map<string, string>` errorList : `ErrorInfo list` Returns: `ErrorInfo list`	Checks that clk is an input port when there are always_ff blocks ast : `VerilogInput` linesLocations : `int list` portMap : `Map<string, string>` errorList : `ErrorInfo list` Returns: `ErrorInfo list`
`checkClkNames ast linesLocations portMap portLocationMap portSizeMap errorList` Full Usage: `checkClkNames ast linesLocations portMap portLocationMap portSizeMap errorList` Parameters: ast : `VerilogInput` linesLocations : `int list` portMap : `Map<string, string>` portLocationMap : `Map<string, int>` portSizeMap : `Map<string, int>` errorList : `ErrorInfo list` Returns: `ErrorInfo list`	Checks if: - no output ports are called clk - clk has width 1 - any of the expressions use clk ast : `VerilogInput` linesLocations : `int list` portMap : `Map<string, string>` portLocationMap : `Map<string, int>` portSizeMap : `Map<string, int>` errorList : `ErrorInfo list` Returns: `ErrorInfo list`
`checkExpressions ast linesLocations wireSizeMap errorList` Full Usage: `checkExpressions ast linesLocations wireSizeMap errorList` Parameters: ast : `VerilogInput` linesLocations : `int list` wireSizeMap : `Map<string, int>` errorList : `ErrorInfo list` Returns: `ErrorInfo list`	Check if expressions are correct - Indexes within range - Numbers are correctly formatted ast : `VerilogInput` linesLocations : `int list` wireSizeMap : `Map<string, int>` errorList : `ErrorInfo list` Returns: `ErrorInfo list`
`checkModuleInstantiations ast linesLocations portSizeMap wireSizeMap project portMap errorList` Full Usage: `checkModuleInstantiations ast linesLocations portSizeMap wireSizeMap project portMap errorList` Parameters: ast : `VerilogInput` linesLocations : `int list` portSizeMap : `Map<string, int>` wireSizeMap : `Map<string, int>` project : `Project` portMap : `Map<string, string>` errorList : `ErrorInfo list` Returns: `ErrorInfo list`	Checks if module instantiation statements are correct: - Does a loaded component exist with the given name? - Are the inputs and outputs the correct width? - Are the portIds correct? - Are all the ports connected? - Are there any duplicate ports? - Make sure inputs are inputs (they have been assigned something), outputs are not driven by anything ast : `VerilogInput` linesLocations : `int list` portSizeMap : `Map<string, int>` wireSizeMap : `Map<string, int>` project : `Project` portMap : `Map<string, string>` errorList : `ErrorInfo list` Returns: `ErrorInfo list`
`checkProceduralAssignments ast linesLocations errorList` Full Usage: `checkProceduralAssignments ast linesLocations errorList` Parameters: ast : `VerilogInput` linesLocations : `int list` errorList : `ErrorInfo list` Returns: `ErrorInfo list`	Checks if always_comb only contains blocking assignments and always_ff only contains nonblocking assignments ast : `VerilogInput` linesLocations : `int list` errorList : `ErrorInfo list` Returns: `ErrorInfo list`
`checkVariablesAlwaysAssigned ast linesLocations portSizeMap wireSizeMap errorList` Full Usage: `checkVariablesAlwaysAssigned ast linesLocations portSizeMap wireSizeMap errorList` Parameters: ast : `VerilogInput` linesLocations : `int list` portSizeMap : `Map<string, int>` wireSizeMap : `Map<string, int>` errorList : `ErrorInfo list` Returns: `ErrorInfo list`	ast : `VerilogInput` linesLocations : `int list` portSizeMap : `Map<string, int>` wireSizeMap : `Map<string, int>` errorList : `ErrorInfo list` Returns: `ErrorInfo list`
`checkVariablesDrivenSimultaneously ast linesLocations errorList` Full Usage: `checkVariablesDrivenSimultaneously ast linesLocations errorList` Parameters: ast : `VerilogInput` linesLocations : `int list` errorList : `ErrorInfo list` Returns: `ErrorInfo list`	Checks if a variable is driven by multiple always blocks or continuous assignments Could be improved if it printed out the variables / marked the error at the location of the variables ast : `VerilogInput` linesLocations : `int list` errorList : `ErrorInfo list` Returns: `ErrorInfo list`
`checkVariablesUsed ast linesLocations portSizeMap wireSizeMap errorList` Full Usage: `checkVariablesUsed ast linesLocations portSizeMap wireSizeMap errorList` Parameters: ast : `VerilogInput` linesLocations : `int list` portSizeMap : `Map<string, int>` wireSizeMap : `Map<string, int>` errorList : `ErrorInfo list` Returns: `ErrorInfo list`	Look for unassigned variables (not outputs, just variables) ast : `VerilogInput` linesLocations : `int list` portSizeMap : `Map<string, int>` wireSizeMap : `Map<string, int>` errorList : `ErrorInfo list` Returns: `ErrorInfo list`
`cycleCheck ast linesLocations portSizeMap wireSizeMap errorList` Full Usage: `cycleCheck ast linesLocations portSizeMap wireSizeMap errorList` Parameters: ast : `VerilogInput` linesLocations : `int list` portSizeMap : `Map<string, int>` wireSizeMap : `Map<string, int>` errorList : `ErrorInfo list` Returns: `ErrorInfo list`	Check for dependency cycles in always_comb blocks and continuous assignments ast : `VerilogInput` linesLocations : `int list` portSizeMap : `Map<string, int>` wireSizeMap : `Map<string, int>` errorList : `ErrorInfo list` Returns: `ErrorInfo list`
`findCycleDFS graph` Full Usage: `findCycleDFS graph` Parameters: graph : `Graph` Returns: `string list option`	Looks for cycles in the general dependency graph using depth first search graph : `Graph` Returns: `string list option`
`getPrimaryWidth portSizeMap primary` Full Usage: `getPrimaryWidth portSizeMap primary` Parameters: portSizeMap : `Map<string, int>` primary : `PrimaryT` Returns: `int`	portSizeMap : `Map<string, int>` primary : `PrimaryT` Returns: `int`
`getVariablesWrittenAfterRead wireAndPortSizeMap linesLocations (rhsVars, errors) node` Full Usage: `getVariablesWrittenAfterRead wireAndPortSizeMap linesLocations (rhsVars, errors) node` Parameters: wireAndPortSizeMap : `Map<string, int>` linesLocations : `int list` rhsVars : `Set<string>` errors : `ErrorInfo list` node : `ASTNode` Returns: `Set<string> * ErrorInfo list`	Helper function for checking if any variable or port being written to after it is read in always_comb blocks. wireAndPortSizeMap : `Map<string, int>` linesLocations : `int list` rhsVars : `Set<string>` errors : `ErrorInfo list` node : `ASTNode` Returns: `Set<string> * ErrorInfo list`