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ASTNode Type

Union cases

Union case Description

AlwaysConstruct AlwaysConstruct

Full Usage: AlwaysConstruct AlwaysConstruct

Parameters:
Item : AlwaysConstruct

Assignment Assignment

Full Usage: Assignment Assignment

Parameters:
Item : Assignment

AssignmentLHS AssignmentLHS

Full Usage: AssignmentLHS AssignmentLHS

Parameters:
Item : AssignmentLHS

Case CaseStatement

Full Usage: Case CaseStatement

Parameters:
Item : CaseStatement

CaseItem CaseItem

Full Usage: CaseItem CaseItem

Parameters:
Item : CaseItem

ContStatement ContinuousAssign

Full Usage: ContStatement ContinuousAssign

Parameters:
Item : ContinuousAssign

Declaration Declaration

Full Usage: Declaration Declaration

Parameters:
Item : Declaration

Expression ExpressionDU

Full Usage: Expression ExpressionDU

Parameters:
Item : ExpressionDU

ForStatement ForStatement

Full Usage: ForStatement ForStatement

Parameters:
Item : ForStatement

IOItem IOItem

Full Usage: IOItem IOItem

Parameters:
Item : IOItem

IfStatement IfStatement

Full Usage: IfStatement IfStatement

Parameters:
Item : IfStatement

Item ItemDU

Full Usage: Item ItemDU

Parameters:
Item : ItemDU

Module Module

Full Usage: Module Module

Parameters:
Item : Module

ModuleInstantiation ModuleInstantiation

Full Usage: ModuleInstantiation ModuleInstantiation

Parameters:
Item : ModuleInstantiation

ModuleItems ModuleItems

Full Usage: ModuleItems ModuleItems

Parameters:
Item : ModuleItems

Number Number

Full Usage: Number Number

Parameters:
Item : Number

ParamDecl ParameterItem

Full Usage: ParamDecl ParameterItem

Parameters:
Item : ParameterItem

ParameterItem ParameterItem

Full Usage: ParameterItem ParameterItem

Parameters:
Item : ParameterItem

Primary PrimaryDU

Full Usage: Primary PrimaryDU

Parameters:
Item : PrimaryDU

Range Range

Full Usage: Range Range

Parameters:
Item : Range

Statement StatementDU

Full Usage: Statement StatementDU

Parameters:
Item : StatementDU

Unary UnaryDU

Full Usage: Unary UnaryDU

Parameters:
Item : UnaryDU

VerilogInput VerilogInput

Full Usage: VerilogInput VerilogInput

Parameters:
Item : VerilogInput

Instance members

Instance member Description

this.IsAlwaysConstruct

Full Usage: this.IsAlwaysConstruct

Returns: bool
Returns: bool

this.IsAssignment

Full Usage: this.IsAssignment

Returns: bool
Returns: bool

this.IsAssignmentLHS

Full Usage: this.IsAssignmentLHS

Returns: bool
Returns: bool

this.IsCase

Full Usage: this.IsCase

Returns: bool
Returns: bool

this.IsCaseItem

Full Usage: this.IsCaseItem

Returns: bool
Returns: bool

this.IsContStatement

Full Usage: this.IsContStatement

Returns: bool
Returns: bool

this.IsDeclaration

Full Usage: this.IsDeclaration

Returns: bool
Returns: bool

this.IsExpression

Full Usage: this.IsExpression

Returns: bool
Returns: bool

this.IsForStatement

Full Usage: this.IsForStatement

Returns: bool
Returns: bool

this.IsIOItem

Full Usage: this.IsIOItem

Returns: bool
Returns: bool

this.IsIfStatement

Full Usage: this.IsIfStatement

Returns: bool
Returns: bool

this.IsItem

Full Usage: this.IsItem

Returns: bool
Returns: bool

this.IsModule

Full Usage: this.IsModule

Returns: bool
Returns: bool

this.IsModuleInstantiation

Full Usage: this.IsModuleInstantiation

Returns: bool
Returns: bool

this.IsModuleItems

Full Usage: this.IsModuleItems

Returns: bool
Returns: bool

this.IsNumber

Full Usage: this.IsNumber

Returns: bool
Returns: bool

this.IsParamDecl

Full Usage: this.IsParamDecl

Returns: bool
Returns: bool

this.IsParameterItem

Full Usage: this.IsParameterItem

Returns: bool
Returns: bool

this.IsPrimary

Full Usage: this.IsPrimary

Returns: bool
Returns: bool

this.IsRange

Full Usage: this.IsRange

Returns: bool
Returns: bool

this.IsStatement

Full Usage: this.IsStatement

Returns: bool
Returns: bool

this.IsUnary

Full Usage: this.IsUnary

Returns: bool
Returns: bool

this.IsVerilogInput

Full Usage: this.IsVerilogInput

Returns: bool
Returns: bool

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