Add one driver changing the fs.Driver array reference. Return a WaveIndex reference. WaveIndex refrences are bound to specific component ports and not unique per driver.

Called after the fs.Drivers array is created. waveComps must contain all components that can be viewed in the wave simulation. This function mutates fs.Drivers adding the correct arrays where these are used. In some cases an array may never be used and therefore is not added. In parallel with this, the function returns an array of WaveIndexT records that reference component ports which can be viewed in a wave simulation. Every WaveIndex references an element of fs.Drivers from which the simulation data is found.

Adds WaveComps, Drivers and WaveIndex fields to a fast simulation. For use by waveform Simulator. Needs to be run after widths are calculated.

Refuse a simulation whose step arrays would not fit, before a byte of them is allocated. Before rather than after, because the arrays ARE what exhausts memory: a check that had to build them first would be the thing it is meant to prevent. Everything it needs is known by then - the flattened design gives every width, and the caller has said how many cycles it wants - so the answer is exact rather than a guess. A Result and not an exception: this is a limit an ordinary user reaches by asking for a long waveform simulation of a big design, so it travels the same path as any other simulation error and is shown the same way, saying what would fit instead.

create a FastComponent data structure with data arrays from a SimulationComponent. numSteps is the number of past clocks data kept - arrays are managed as circular buffers.

This function will create the initial FastSimulation data structure. It may not complete this. In which case fields NumCreateSteps and NumCreateStepsDone will not be equal.

Convert the data in the a SimulationGraph, created from the circuit into a final GatherData structure suitable for simulation stored as a set of maps Calls createFlattenedSimulation as first step.

Use the Outputs links from the original SimulationComponents in gather to link together the data arrays of the FastComponents. InputLinks[i] array is set equal to the correct driving Outputs array so that Input i reads the data reduced by the correct output of the component that drives it. The main work is dealing with custom components which represent whole design sheets with recursively defined component graphs The custom component itself is not linked, and does not exist as a simulatable FastComponent. Note: custom components are linked in later as unsimulatable placeholders to allow wave simulation to access ports Instead its CustomSimulationGraph Input and Output components are linked to the components that connect the corresponding inputs and outputs of the custom component.

Changes all the custom component in and out StepArray links so they point to the correct drivers. (fid, fc) must be a custom component. Called after the simulation has been fully constructed and linked.

The most clock cycles of a design costing this much that will be allowed, whichever of the two budgets binds first. Used both to refuse a simulation and to say in the waveform simulator's configuration what may be asked for, so that the two cannot disagree.

Start drawing ≤32-bit step arrays from arena slabs. Callers must pair this with finishStepArena however the build ends, or the next truth-table build would draw from a slab nobody meant it to share.

One clock cycle of a bus of this width, in bytes of the memory it is stored in. See above, and keep in step with makeIOArrayW immediately below: they describe the same allocation.

What one clock cycle of this design will cost, worked out from the flattened design before the arrays exist. createInitFastCompPhase allocates exactly one step array per output port of every component in AllComps, so that is what is counted here. AllComps includes the custom components, whose output arrays are allocated and then replaced by links to the arrays inside them (linkFastCustomComponentsToDriverArrays). Those arrays come out of the step-array arena along with everything else, and arena space is not reclaimed until the whole simulation goes - so this count is exactly what a built simulation occupies, the replaced quarter included, not an estimate of it. The per-step State array is counted too. Only RAMs ever write it, but createFastComponent allocates one for every component that could be synchronous - customs included - so on a register-heavy design it is real memory, and the estimate that omitted it said a design was smaller than it is.