last step number (starting from 0) which is simulated.

This contains all components in the sheets of the simulation indexed by ComponentId. Subsheet components are indexed only once. Contrast this with Fast Components - which have the design expanded out with one per instance: the different versions correspond to distinct access paths.

Connections on simulated sheets indexed by directly connected port. Each connection appears twice.

Each driver represents one output with its data

clocked components

Fast components: this array is longer than FOrderedComps because it contains IOlabel components that are redundant in the simulation. It doe snot contain custom Components

constants

Custom Components.

look up from output port of custom component to the relevant Output component

top-level inputs to the simulation

which is the active component for each set of labels?

list of deferred links driven from inactive IOlabls - at end of linkage the corresponding active IOLabel can be substituted as driver an dthe link made

Components that will be reduced in order allowing sequential reduction to implement simulation

Map from a component to its SimulationComponent and Access Path

GatherData from which this simulation was made

Maximum size of simulation arrays - after which they form a circular buffer

Total number of step arrays (= drivers)

Map from a component's Access Path to the run-time unique SimSheetName of the sheet

Map from SimSheetName to the parent sheet CustomComponent, or None if the sheet is top-level

Circuit simulated (sheet and all dependencies)

The root sheet being simulated

Total size of the output arrays per time-step.

Fast components: this map is longer than FComps because it contains Custom components not used by Fast simulation but needed in Waveform simulation

Each wave index represents one component port with associated driver and data