SheetCreator Module
Types
Type | Description |
Functions and values
Function or value | Description |
Full Usage:
addAssignment assignment bits varToCompMap
Parameters:
BitMapping
bits : List<BitMapping>
varToCompMap : 'a
Returns: BitMapping list
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Full Usage:
buildExpressionComponent rhs width
Parameters:
ExpressionCompilable
width : int
Returns: Component
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Full Usage:
collectWiresLHS assignments
Parameters:
ItemT list
Returns: AssignmentLHST list
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Full Usage:
compileModule node varToCompMap ioToCompMap varSizeMap initialCircuits project
Parameters:
ASTNode
varToCompMap : Map<string, Component>
ioToCompMap : Map<string, Component>
varSizeMap : Map<string, int>
initialCircuits : Map<string, Circuit>
project : Project
Returns: Map<string, Circuit>
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Full Usage:
concatenateCanvasStates (arg1, arg2) (arg3, arg4)
Parameters:
Component list
arg1 : Connection list
arg2 : Component list
arg3 : Connection list
Returns: CanvasState
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Full Usage:
createComponent compType name
Parameters:
ComponentType
name : string
Returns: Component
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Full Usage:
createComponent' id compType name inputPorts outputPorts
Parameters:
string
compType : ComponentType
name : string
inputPorts : Port list
outputPorts : Port list
Returns: Component
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Full Usage:
createSheet input project
Parameters:
VerilogInput
project : Project
Returns: Component list * List<Connection>
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Full Usage:
fixCanvasState (arg1, arg2)
Parameters:
Component list
arg1 : Connection list
Returns: Component list * List<Connection>
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Full Usage:
fixConsecutiveWires (arg1, arg2)
Parameters:
Component list
arg1 : Connection list
Returns: Component list * List<Connection>
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Full Usage:
getCombinationalVars ast project
Parameters:
VerilogInput
project : Project
Returns: string list
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Full Usage:
getExprWidths varSizeMap expr'
Parameters:
Map<string, int>
expr' : ExpressionT
Returns: ExpressionCompilable
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Full Usage:
getWireToCompMap lhs ioAndWireToCompMap
Parameters:
AssignmentLHST
ioAndWireToCompMap : Map<string, Component>
Returns: Map<string, Component>
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Full Usage:
isCircuitValid' comps conns
Parameters:
Component list
conns : Connection list
Returns: bool
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Full Usage:
mainExpressionCircuitBuilder expr ioAndWireToCompMap varSizeMap target
Parameters:
ExpressionT
ioAndWireToCompMap : Map<string, Component>
varSizeMap : Map<string, int>
target : int
Returns: Circuit
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Full Usage:
mergeIfElse lst1 lst2 varToCompMap
Parameters:
List<BitMapping>
lst2 : List<BitMapping>
varToCompMap : 'a
Returns: List<Option<BitMapping> * Option<BitMapping>>
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Full Usage:
sliceFromBits lhs ioAndWireToCompMap varSizeMap
Parameters:
AssignmentLHST
ioAndWireToCompMap : Map<string, Component>
varSizeMap : Map<string, int>
Returns: Slice
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