SheetCreator (issie)

SheetCreator Module

Namespace: global
Assembly: Renderer.dll

Types

Type	Description
BitMapping
Circuit
ExprKind	stores the expression along with the self determined width (MinWidth) and the contect determined Width
ExpressionCompilable
LHSType
Slice
UnaryCompilable
UnaryKind

Functions and values

Function or value	Description
`addAssignment assignment bits varToCompMap` Full Usage: `addAssignment assignment bits varToCompMap` Parameters: assignment : `BitMapping` bits : `List<BitMapping>` varToCompMap : `'a` Returns: `BitMapping list`	assignment : `BitMapping` bits : `List<BitMapping>` varToCompMap : `'a` Returns: `BitMapping list`
`attachArrayToOutput arrayToCompMap circuitList portName` Full Usage: `attachArrayToOutput arrayToCompMap circuitList portName` Parameters: arrayToCompMap : `Map<string, Component list>` circuitList : `Circuit list` portName : `string` Returns: `CanvasState`	arrayToCompMap : `Map<string, Component list>` circuitList : `Circuit list` portName : `string` Returns: `CanvasState`
`attachToOutput ioAndWireToCompMap ioToCompMap circuit portName` Full Usage: `attachToOutput ioAndWireToCompMap ioToCompMap circuit portName` Parameters: ioAndWireToCompMap : `Map<string, Component>` ioToCompMap : `Map<string, Component>` circuit : `Circuit` portName : `string` Returns: `CanvasState`	Attach the merged circuits to the correct output port ioAndWireToCompMap : `Map<string, Component>` ioToCompMap : `Map<string, Component>` circuit : `Circuit` portName : `string` Returns: `CanvasState`
`attachToOutput' ioAndWireToCompMap ioToCompMap (circuit, portName, slice, lhsType)` Full Usage: `attachToOutput' ioAndWireToCompMap ioToCompMap (circuit, portName, slice, lhsType)` Parameters: ioAndWireToCompMap : `Map<string, Component>` ioToCompMap : `Map<string, Component>` circuit : `Circuit` portName : `string` slice : `Slice` lhsType : `LHSType` Returns: `CanvasState`	Attach the merged circuits to the correct output port ioAndWireToCompMap : `Map<string, Component>` ioToCompMap : `Map<string, Component>` circuit : `Circuit` portName : `string` slice : `Slice` lhsType : `LHSType` Returns: `CanvasState`
`buildExpressionComponent rhs width` Full Usage: `buildExpressionComponent rhs width` Parameters: rhs : `ExpressionCompilable` width : `int` Returns: `Component`	Extract component type and name from expression (type ExpressionT) Create the component using the createComponent function rhs : `ExpressionCompilable` width : `int` Returns: `Component`
`buildFixedShiftCircuit inputCircuit shiftNo shiftType` Full Usage: `buildFixedShiftCircuit inputCircuit shiftNo shiftType` Parameters: inputCircuit : `Circuit` shiftNo : `int` shiftType : `ShiftComponentType` Returns: `Circuit`	inputCircuit : `Circuit` shiftNo : `int` shiftType : `ShiftComponentType` Returns: `Circuit`
`buildMuxTreeCircuit inputs sel outputWidth` Full Usage: `buildMuxTreeCircuit inputs sel outputWidth` Parameters: inputs : `Circuit list` sel : `Circuit` outputWidth : `int` Returns: `Circuit`	inputs : `Circuit list` sel : `Circuit` outputWidth : `int` Returns: `Circuit`
`collectInputAndWireComps ioAndWireToCompMap` Full Usage: `collectInputAndWireComps ioAndWireToCompMap` Parameters: ioAndWireToCompMap : `Map<string, Component>` Returns: `Component list`	ioAndWireToCompMap : `Map<string, Component>` Returns: `Component list`
`collectWiresLHS assignments` Full Usage: `collectWiresLHS assignments` Parameters: assignments : `ItemDU list` Returns: `AssignmentLHS list`	assignments : `ItemDU list` Returns: `AssignmentLHS list`
`compileModule node varToCompMap ioToCompMap varSizeMap paramMap arraySizeMap arrayToCompMap initialCircuits initialArrayCircuits project compName model dispatch` Full Usage: `compileModule node varToCompMap ioToCompMap varSizeMap paramMap arraySizeMap arrayToCompMap initialCircuits initialArrayCircuits project compName model dispatch` Parameters: node : `ASTNode` varToCompMap : `Map<string, Component>` ioToCompMap : `Map<string, Component>` varSizeMap : `Map<string, int>` paramMap : `Map<string, int>` arraySizeMap : `Map<string, (int * int array)>` arrayToCompMap : `Map<string, Component list>` initialCircuits : `Map<string, Circuit>` initialArrayCircuits : `Map<string, Circuit list>` project : `Project` compName : `string` model : `Model` dispatch : `Msg -> unit` Returns: `Map<string, Circuit> * Map<string, Circuit list>`	node : `ASTNode` varToCompMap : `Map<string, Component>` ioToCompMap : `Map<string, Component>` varSizeMap : `Map<string, int>` paramMap : `Map<string, int>` arraySizeMap : `Map<string, (int * int array)>` arrayToCompMap : `Map<string, Component list>` initialCircuits : `Map<string, Circuit>` initialArrayCircuits : `Map<string, Circuit list>` project : `Project` compName : `string` model : `Model` dispatch : `Msg -> unit` Returns: `Map<string, Circuit> * Map<string, Circuit list>`
`compileModule' node varToCompMap ioToCompMap varSizeMap paramMap arraySizeMap arrayToCompMap` Full Usage: `compileModule' node varToCompMap ioToCompMap varSizeMap paramMap arraySizeMap arrayToCompMap` Parameters: node : `ASTNode` varToCompMap : `Map<string, Component>` ioToCompMap : `Map<string, 'a>` varSizeMap : `Map<string, int>` paramMap : `Map<string, int>` arraySizeMap : `Map<string, (int * int array)>` arrayToCompMap : `Map<string, Component list>` Returns: `Map<string, List<BitMapping>>`	returns a mapping from lhs variable name -> bits -> rhs final circuit maybe store the bits in a sorted array instead of a map node : `ASTNode` varToCompMap : `Map<string, Component>` ioToCompMap : `Map<string, 'a>` varSizeMap : `Map<string, int>` paramMap : `Map<string, int>` arraySizeMap : `Map<string, (int * int array)>` arrayToCompMap : `Map<string, Component list>` Returns: `Map<string, List<BitMapping>>`
`concatenateCanvasStates (arg1, arg2) (arg3, arg4)` Full Usage: `concatenateCanvasStates (arg1, arg2) (arg3, arg4)` Parameters: arg0 : `Component list` arg1 : `Connection list` arg2 : `Component list` arg3 : `Connection list` Returns: `CanvasState`	arg0 : `Component list` arg1 : `Connection list` arg2 : `Component list` arg3 : `Connection list` Returns: `CanvasState`
`createArrayCircuit primary ioAndWireToCompMap arraySizeMap arrayCompList` Full Usage: `createArrayCircuit primary ioAndWireToCompMap arraySizeMap arrayCompList` Parameters: primary : `PrimaryDU` ioAndWireToCompMap : `Map<string, Component>` arraySizeMap : `Map<string, (int * int array)>` arrayCompList : `Component list` Returns: `Circuit`	Creates component for array access primary : `PrimaryDU` ioAndWireToCompMap : `Map<string, Component>` arraySizeMap : `Map<string, (int * int array)>` arrayCompList : `Component list` Returns: `Circuit`
`createComponent compType name` Full Usage: `createComponent compType name` Parameters: compType : `ComponentType` name : `string` Returns: `Component`	Main component creation function Find all the parameters required for component creation based on the component Type and the name(label) given Returns the created component compType : `ComponentType` name : `string` Returns: `Component`
`createComponent' id compType name inputPorts outputPorts` Full Usage: `createComponent' id compType name inputPorts outputPorts` Parameters: id : `string` compType : `ComponentType` name : `string` inputPorts : `Port list` outputPorts : `Port list` Returns: `Component`	Create a component (type: Component) based on the parameters given id : `string` compType : `ComponentType` name : `string` inputPorts : `Port list` outputPorts : `Port list` Returns: `Component`
`createConnection source target` Full Usage: `createConnection source target` Parameters: source : `Port` target : `Port` Returns: `Connection`	Connect source with target returning the connection (type: Connection) source : `Port` target : `Port` Returns: `Connection`
`createIOComponent item ioType oldMap paramMap` Full Usage: `createIOComponent item ioType oldMap paramMap` Parameters: item : `ItemDU` ioType : `DeclarationDU` oldMap : `(string * Component) list` paramMap : `Map<string, int>` Returns: `(string * Component) list`	item : `ItemDU` ioType : `DeclarationDU` oldMap : `(string * Component) list` paramMap : `Map<string, int>` Returns: `(string * Component) list`
`createNumberCircuit number` Full Usage: `createNumberCircuit number` Parameters: number : `Number` Returns: `Circuit`	Creates the correct component based on the number and returns a circuit with that component number : `Number` Returns: `Circuit`
`createPort hostId portType portNumber` Full Usage: `createPort hostId portType portNumber` Parameters: hostId : `string` portType : `PortType` portNumber : `int option` Returns: `Port`	Create a port (type: Port) based on the parameters given hostId : `string` portType : `PortType` portNumber : `int option` Returns: `Port`
`createPortList ofType number hostId` Full Usage: `createPortList ofType number hostId` Parameters: ofType : `PortType` number : `int` hostId : `string` Returns: `Port list`	ofType : `PortType` number : `int` hostId : `string` Returns: `Port list`
`createPrimaryCircuit primary ioAndWireToCompMap varSizeMap paramMap` Full Usage: `createPrimaryCircuit primary ioAndWireToCompMap varSizeMap paramMap` Parameters: primary : `PrimaryDU` ioAndWireToCompMap : `Map<string, Component>` varSizeMap : `Map<string, int>` paramMap : `Map<string, int>` Returns: `Circuit`	Finds the correct component based on the name of input/wire creates a circuit with that component (and if required a busSel component connected to it to return the correct slice) and returns that circuit primary : `PrimaryDU` ioAndWireToCompMap : `Map<string, Component>` varSizeMap : `Map<string, int>` paramMap : `Map<string, int>` Returns: `Circuit`
`createRegisterArray var arraySizeMap` Full Usage: `createRegisterArray var arraySizeMap` Parameters: var : `string` arraySizeMap : `Map<string, (int * int[])>` Returns: `Component list`	Helper function to see if an array is written to multiple times - determines whether it synthesises to a memory or registers var : `string` arraySizeMap : `Map<string, (int * int[])>` Returns: `Component list`
`createSheet veriloginput project model dispatch` Full Usage: `createSheet veriloginput project model dispatch` Parameters: veriloginput : `VerilogInput` project : `Project` model : `Model` dispatch : `Msg -> unit` Returns: `CanvasState`	veriloginput : `VerilogInput` project : `Project` model : `Model` dispatch : `Msg -> unit` Returns: `CanvasState`
`dfsTraversal graph componentMap connections parents` Full Usage: `dfsTraversal graph componentMap connections parents` Parameters: graph : `Map<string, List<string>>` componentMap : `Map<string, Component>` connections : `List<Connection>` parents : `Set<string>` Returns: `Map<string, Component> * List<Connection>`	graph : `Map<string, List<string>>` componentMap : `Map<string, Component>` connections : `List<Connection>` parents : `Set<string>` Returns: `Map<string, Component> * List<Connection>`
`evalExprWithVarsAndParams expr paramMap varSizeMap` Full Usage: `evalExprWithVarsAndParams expr paramMap varSizeMap` Parameters: expr : `ExpressionDU` paramMap : `Map<string, int>` varSizeMap : `Map<string, int>` Returns: `int`	expr : `ExpressionDU` paramMap : `Map<string, int>` varSizeMap : `Map<string, int>` Returns: `int`
`extendCircuit target circuit` Full Usage: `extendCircuit target circuit` Parameters: target : `int` circuit : `Circuit` Returns: `Circuit`	target : `int` circuit : `Circuit` Returns: `Circuit`
`extractCircuit (arg1, arg2, arg3, arg4)` Full Usage: `extractCircuit (arg1, arg2, arg3, arg4)` Parameters: arg0 : `Circuit` arg1 : `string` arg2 : `Slice` arg3 : `LHSType` Returns: `Circuit`	arg0 : `Circuit` arg1 : `string` arg2 : `Slice` arg3 : `LHSType` Returns: `Circuit`
`fixCanvasState (arg1, arg2)` Full Usage: `fixCanvasState (arg1, arg2)` Parameters: arg0 : `Component list` arg1 : `Connection list` Returns: `Component list * List<Connection>`	Helper function to resolve conflicts in labels (must be distinct) and component locations on canvas (must not overlap_) arg0 : `Component list` arg1 : `Connection list` Returns: `Component list * List<Connection>`
`fixConsecutiveWires (arg1, arg2)` Full Usage: `fixConsecutiveWires (arg1, arg2)` Parameters: arg0 : `Component list` arg1 : `Connection list` Returns: `Component list * List<Connection>`	arg0 : `Component list` arg1 : `Connection list` Returns: `Component list * List<Connection>`
`getClockedVars ast` Full Usage: `getClockedVars ast` Parameters: ast : `VerilogInput` Returns: `string list`	ast : `VerilogInput` Returns: `string list`
`getCombinationalVars ast project` Full Usage: `getCombinationalVars ast project` Parameters: ast : `VerilogInput` project : `Project` Returns: `string list`	ast : `VerilogInput` project : `Project` Returns: `string list`
`getExprWidths varSizeMap paramMap expr'` Full Usage: `getExprWidths varSizeMap paramMap expr'` Parameters: varSizeMap : `Map<string, int>` paramMap : `Map<string, int>` expr' : `ExpressionDU` Returns: `ExpressionCompilable`	varSizeMap : `Map<string, int>` paramMap : `Map<string, int>` expr' : `ExpressionDU` Returns: `ExpressionCompilable`
`getIOtoComponentMap ioDecls paramMap` Full Usage: `getIOtoComponentMap ioDecls paramMap` Parameters: ioDecls : `ItemDU list` paramMap : `Map<string, int>` Returns: `Map<string, Component>`	Return a Map for input and output ports where string -> port name. It is necessary in order to find components when building circuits for assignments ioDecls : `ItemDU list` paramMap : `Map<string, int>` Returns: `Map<string, Component>`
`getInitialMapAndCircuits veriloginput project paramMap` Full Usage: `getInitialMapAndCircuits veriloginput project paramMap` Parameters: veriloginput : `VerilogInput` project : `Project` paramMap : `Map<string, int>` Returns: `Map<string, Component> * Map<string, Component> * Map<string, int> * Map<string, Circuit> * Map<string, Circuit list> * string list * Map<string, (int * int array)> * Map<string, Component list>`	veriloginput : `VerilogInput` project : `Project` paramMap : `Map<string, int>` Returns: `Map<string, Component> * Map<string, Component> * Map<string, int> * Map<string, Circuit> * Map<string, Circuit list> * string list * Map<string, (int * int array)> * Map<string, Component list>`
`getWidthFromRange range paramMap` Full Usage: `getWidthFromRange range paramMap` Parameters: range : `Range option` paramMap : `Map<string, int>` Returns: `int`	Helper function to find a port's width from the range definition of IODecl range : `Range option` paramMap : `Map<string, int>` Returns: `int`
`getWireToCompMap lhs ioAndWireToCompMap` Full Usage: `getWireToCompMap lhs ioAndWireToCompMap` Parameters: lhs : `AssignmentLHS` ioAndWireToCompMap : `Map<string, Component>` Returns: `Map<string, Component>`	Return a Map for wires where string -> wire name. It is necessary in order to find wire components when building circuits for assignments lhs : `AssignmentLHS` ioAndWireToCompMap : `Map<string, Component>` Returns: `Map<string, Component>`
`isCircuitValid circuit varToCompMap` Full Usage: `isCircuitValid circuit varToCompMap` Parameters: circuit : `Circuit` varToCompMap : `Map<string, Component>` Returns: `bool`	debug: circuit : `Circuit` varToCompMap : `Map<string, Component>` Returns: `bool`
`isCircuitValid' comps conns` Full Usage: `isCircuitValid' comps conns` Parameters: comps : `Component list` conns : `Connection list` Returns: `bool`	debug: comps : `Component list` conns : `Connection list` Returns: `bool`
`isOutputComponent comp` Full Usage: `isOutputComponent comp` Parameters: comp : `Component` Returns: `bool`	comp : `Component` Returns: `bool`
`isSameModuleIgnoringParams name1 name2` Full Usage: `isSameModuleIgnoringParams name1 name2` Parameters: name1 : `string` name2 : `string` Returns: `bool`	name1 : `string` name2 : `string` Returns: `bool`
`joinCircuits inCircuits inPorts topCircuit` Full Usage: `joinCircuits inCircuits inPorts topCircuit` Parameters: inCircuits : `Circuit list` inPorts : `Port list` topCircuit : `Circuit` Returns: `Circuit`	Join input ports of topCircuit with inCircuits inCircuits : `Circuit list` inPorts : `Port list` topCircuit : `Circuit` Returns: `Circuit`
`joinWithMerge lst` Full Usage: `joinWithMerge lst` Parameters: lst : `(Circuit * string * Slice * LHSType) list` Returns: `Circuit * string * Slice * LHSType`	Join a list of circuits with MergeWires components lst : `(Circuit * string * Slice * LHSType) list` Returns: `Circuit * string * Slice * LHSType`
`joinWithMerge' circuits` Full Usage: `joinWithMerge' circuits` Parameters: circuits : `Circuit list` Returns: `Circuit`	circuits : `Circuit list` Returns: `Circuit`
`mainExpressionCircuitBuilder expr ioAndWireToCompMap varSizeMap paramMap target arraySizeMap arrayToCompMap` Full Usage: `mainExpressionCircuitBuilder expr ioAndWireToCompMap varSizeMap paramMap target arraySizeMap arrayToCompMap` Parameters: expr : `ExpressionDU` ioAndWireToCompMap : `Map<string, Component>` varSizeMap : `Map<string, int>` paramMap : `Map<string, int>` target : `int` arraySizeMap : `Map<string, (int * int array)>` arrayToCompMap : `Map<string, Component list>` Returns: `Circuit`	The main circuit creation function called with the RHS of an assignment as a parameter Contains 6 recursive functions which eventually build the whole RHS expression The starting point is the buildExpressionCircuit rec function target is 0 if there is no lhs expr : `ExpressionDU` ioAndWireToCompMap : `Map<string, Component>` varSizeMap : `Map<string, int>` paramMap : `Map<string, int>` target : `int` arraySizeMap : `Map<string, (int * int array)>` arrayToCompMap : `Map<string, Component list>` Returns: `Circuit`
`merge2Circuits c1 c2` Full Usage: `merge2Circuits c1 c2` Parameters: c1 : `Circuit` c2 : `Circuit` Returns: `Circuit`	c1 : `Circuit` c2 : `Circuit` Returns: `Circuit`
`mergeIfElse lst1 lst2 varToCompMap` Full Usage: `mergeIfElse lst1 lst2 varToCompMap` Parameters: lst1 : `List<BitMapping>` lst2 : `List<BitMapping>` varToCompMap : `'a` Returns: `List<Option<BitMapping> * Option<BitMapping>>`	lst1 : `List<BitMapping>` lst2 : `List<BitMapping>` varToCompMap : `'a` Returns: `List<Option<BitMapping> * Option<BitMapping>>`
`multiplexerCircuit inputs condition defaultInput` Full Usage: `multiplexerCircuit inputs condition defaultInput` Parameters: inputs : `List<bigint * Circuit>` condition : `Circuit` defaultInput : `Circuit` Returns: `Circuit`	inputs : `List<bigint * Circuit>` condition : `Circuit` defaultInput : `Circuit` Returns: `Circuit`
`multiplexerNto1Circuit inputs sel` Full Usage: `multiplexerNto1Circuit inputs sel` Parameters: inputs : `List<Circuit>` sel : `Circuit` Returns: `Circuit`	takes in n - number of inputs, must be a power of 2 circuit being returned has N (bus) data inputs and 1 select inputs : `List<Circuit>` sel : `Circuit` Returns: `Circuit`
`nextPowerOfTwo value` Full Usage: `nextPowerOfTwo value` Parameters: value : `int` Returns: `int`	value : `int` Returns: `int`
`overlaps slice1 slice2` Full Usage: `overlaps slice1 slice2` Parameters: slice1 : `Slice` slice2 : `Slice` Returns: `bool`	slice1 : `Slice` slice2 : `Slice` Returns: `bool`
`parseParamName name` Full Usage: `parseParamName name` Parameters: name : `string` Returns: `string * string list`	name : `string` Returns: `string * string list`
`sliceCircuit circuit width lsb` Full Usage: `sliceCircuit circuit width lsb` Parameters: circuit : `Circuit` width : `int` lsb : `int` Returns: `Circuit`	circuit : `Circuit` width : `int` lsb : `int` Returns: `Circuit`
`sliceFromBits lhs ioAndWireToCompMap varSizeMap paramMap` Full Usage: `sliceFromBits lhs ioAndWireToCompMap varSizeMap paramMap` Parameters: lhs : `AssignmentLHS` ioAndWireToCompMap : `Map<string, Component>` varSizeMap : `Map<string, int>` paramMap : `Map<string, int>` Returns: `Slice`	Extract MSB,LSB from assignment and return as a Slice type Slice = {MSB:int, LSB:int} lhs : `AssignmentLHS` ioAndWireToCompMap : `Map<string, Component>` varSizeMap : `Map<string, int>` paramMap : `Map<string, int>` Returns: `Slice`
`sliceFromBitsArray lhs arraySizeMap` Full Usage: `sliceFromBitsArray lhs arraySizeMap` Parameters: lhs : `AssignmentLHS` arraySizeMap : `Map<string, (int * int array)>` Returns: `Slice`	lhs : `AssignmentLHS` arraySizeMap : `Map<string, (int * int array)>` Returns: `Slice`
`sliceFromBitsPrimary primary ioAndWireToCompMap varSizeMap paramMap` Full Usage: `sliceFromBitsPrimary primary ioAndWireToCompMap varSizeMap paramMap` Parameters: primary : `PrimaryDU` ioAndWireToCompMap : `Map<string, Component>` varSizeMap : `Map<string, int>` paramMap : `Map<string, int>` Returns: `Slice`	primary : `PrimaryDU` ioAndWireToCompMap : `Map<string, Component>` varSizeMap : `Map<string, int>` paramMap : `Map<string, int>` Returns: `Slice`
`sliceFromWordArray lhs varSizeMap arraySizeMap` Full Usage: `sliceFromWordArray lhs varSizeMap arraySizeMap` Parameters: lhs : `AssignmentLHS` varSizeMap : `Map<string, int>` arraySizeMap : `Map<string, (int * int array)>` Returns: `int`	lhs : `AssignmentLHS` varSizeMap : `Map<string, int>` arraySizeMap : `Map<string, (int * int array)>` Returns: `int`