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SheetCreator Module

Types

Type Description

BitMapping

Circuit

ExpressionCompilable

stores the expression along with the self determined width (MinWidth) and the contect determined Width

LHSType

Slice

UnaryCompilable

Functions and values

Function or value Description

addAssignment assignment bits varToCompMap

Full Usage: addAssignment assignment bits varToCompMap

Parameters:
Returns: BitMapping list
assignment : BitMapping
bits : List<BitMapping>
varToCompMap : 'a
Returns: BitMapping list

attachToOutput ioAndWireToCompMap ioToCompMap circuit portName

Full Usage: attachToOutput ioAndWireToCompMap ioToCompMap circuit portName

Parameters:
Returns: CanvasState

Attach the merged circuits to the correct output port

ioAndWireToCompMap : Map<string, Component>
ioToCompMap : Map<string, Component>
circuit : Circuit
portName : string
Returns: CanvasState

attachToOutput' ioAndWireToCompMap ioToCompMap (circuit, portName, slice, lhsType)

Full Usage: attachToOutput' ioAndWireToCompMap ioToCompMap (circuit, portName, slice, lhsType)

Parameters:
Returns: CanvasState

Attach the merged circuits to the correct output port

ioAndWireToCompMap : Map<string, Component>
ioToCompMap : Map<string, Component>
circuit : Circuit
portName : string
slice : Slice
lhsType : LHSType
Returns: CanvasState

buildExpressionComponent rhs width

Full Usage: buildExpressionComponent rhs width

Parameters:
Returns: Component

Extract component type and name from expression (type ExpressionT) Create the component using the createComponent function

rhs : ExpressionCompilable
width : int
Returns: Component

collectInputAndWireComps ioAndWireToCompMap

Full Usage: collectInputAndWireComps ioAndWireToCompMap

Parameters:
Returns: Component list
ioAndWireToCompMap : Map<string, Component>
Returns: Component list

collectWiresLHS assignments

Full Usage: collectWiresLHS assignments

Parameters:
    assignments : ItemT list

Returns: AssignmentLHST list
assignments : ItemT list
Returns: AssignmentLHST list

compileModule node varToCompMap ioToCompMap varSizeMap initialCircuits project

Full Usage: compileModule node varToCompMap ioToCompMap varSizeMap initialCircuits project

Parameters:
Returns: Map<string, Circuit>
node : ASTNode
varToCompMap : Map<string, Component>
ioToCompMap : Map<string, Component>
varSizeMap : Map<string, int>
initialCircuits : Map<string, Circuit>
project : Project
Returns: Map<string, Circuit>

compileModule' node varToCompMap ioToCompMap varSizeMap

Full Usage: compileModule' node varToCompMap ioToCompMap varSizeMap

Parameters:
Returns: Map<string, List<BitMapping>>

returns a mapping from lhs variable name -> bits -> rhs final circuit maybe store the bits in a sorted array instead of a map

node : ASTNode
varToCompMap : Map<string, Component>
ioToCompMap : Map<string, 'a>
varSizeMap : Map<string, int>
Returns: Map<string, List<BitMapping>>

concatenateCanvasStates (arg1, arg2) (arg3, arg4)

Full Usage: concatenateCanvasStates (arg1, arg2) (arg3, arg4)

Parameters:
Returns: CanvasState
arg0 : Component list
arg1 : Connection list
arg2 : Component list
arg3 : Connection list
Returns: CanvasState

createComponent compType name

Full Usage: createComponent compType name

Parameters:
Returns: Component

Main component creation function Find all the parameters required for component creation based on the component Type and the name(label) given Returns the created component

compType : ComponentType
name : string
Returns: Component

createComponent' id compType name inputPorts outputPorts

Full Usage: createComponent' id compType name inputPorts outputPorts

Parameters:
Returns: Component

Create a component (type: Component) based on the parameters given

id : string
compType : ComponentType
name : string
inputPorts : Port list
outputPorts : Port list
Returns: Component

createConnection source target

Full Usage: createConnection source target

Parameters:
Returns: Connection

Connect source with target returning the connection (type: Connection)

source : Port
target : Port
Returns: Connection

createIOComponent item ioType oldMap

Full Usage: createIOComponent item ioType oldMap

Parameters:
Returns: (string * Component) list
item : ItemT
ioType : string
oldMap : (string * Component) list
Returns: (string * Component) list

createNumberCircuit number

Full Usage: createNumberCircuit number

Parameters:
Returns: Circuit

Creates the correct component based on the number and returns a circuit with that component

number : NumberT
Returns: Circuit

createPort hostId portType portNumber

Full Usage: createPort hostId portType portNumber

Parameters:
    hostId : string
    portType : PortType
    portNumber : int option

Returns: Port

Create a port (type: Port) based on the parameters given

hostId : string
portType : PortType
portNumber : int option
Returns: Port

createPortList ofType number hostId

Full Usage: createPortList ofType number hostId

Parameters:
    ofType : PortType
    number : int
    hostId : string

Returns: Port list
ofType : PortType
number : int
hostId : string
Returns: Port list

createPrimaryCircuit primary ioAndWireToCompMap varSizeMap

Full Usage: createPrimaryCircuit primary ioAndWireToCompMap varSizeMap

Parameters:
Returns: Circuit

Finds the correct component based on the name of input/wire creates a circuit with that component (and if required a busSel component connected to it to return the correct slice) and returns that circuit

primary : PrimaryT
ioAndWireToCompMap : Map<string, Component>
varSizeMap : Map<string, int>
Returns: Circuit

createSheet input project

Full Usage: createSheet input project

Parameters:
Returns: Component list * List<Connection>
input : VerilogInput
project : Project
Returns: Component list * List<Connection>

dfsTraversal graph componentMap connections parents

Full Usage: dfsTraversal graph componentMap connections parents

Parameters:
Returns: Map<string, Component> * List<Connection>
graph : Map<string, List<string>>
componentMap : Map<string, Component>
connections : List<Connection>
parents : Set<string>
Returns: Map<string, Component> * List<Connection>

extendCircuit target circuit

Full Usage: extendCircuit target circuit

Parameters:
Returns: Circuit
target : int
circuit : Circuit
Returns: Circuit

extractCircuit (arg1, arg2, arg3, arg4)

Full Usage: extractCircuit (arg1, arg2, arg3, arg4)

Parameters:
Returns: Circuit
arg0 : Circuit
arg1 : string
arg2 : Slice
arg3 : LHSType
Returns: Circuit

fixCanvasState (arg1, arg2)

Full Usage: fixCanvasState (arg1, arg2)

Parameters:
Returns: Component list * List<Connection>

Helper function to resolve conflicts in labels (must be distinct) and component locations on canvas (must not overlap_)

arg0 : Component list
arg1 : Connection list
Returns: Component list * List<Connection>

fixConsecutiveWires (arg1, arg2)

Full Usage: fixConsecutiveWires (arg1, arg2)

Parameters:
Returns: Component list * List<Connection>
arg0 : Component list
arg1 : Connection list
Returns: Component list * List<Connection>

getClockedVars ast

Full Usage: getClockedVars ast

Parameters:
Returns: string list
ast : VerilogInput
Returns: string list

getCombinationalVars ast project

Full Usage: getCombinationalVars ast project

Parameters:
Returns: string list
ast : VerilogInput
project : Project
Returns: string list

getExprWidths varSizeMap expr'

Full Usage: getExprWidths varSizeMap expr'

Parameters:
Returns: ExpressionCompilable
varSizeMap : Map<string, int>
expr' : ExpressionT
Returns: ExpressionCompilable

getIOtoComponentMap ioDecls

Full Usage: getIOtoComponentMap ioDecls

Parameters:
Returns: Map<string, Component>

Return a Map for input and output ports where string -> port name. It is necessary in order to find components when building circuits for assignments

ioDecls : ItemT list
Returns: Map<string, Component>

getWidthFromRange range

Full Usage: getWidthFromRange range

Parameters:
Returns: int

Helper function to find a port's width from the range definition of IODecl

range : RangeT option
Returns: int

getWireToCompMap lhs ioAndWireToCompMap

Full Usage: getWireToCompMap lhs ioAndWireToCompMap

Parameters:
Returns: Map<string, Component>

Return a Map for wires where string -> wire name. It is necessary in order to find wire components when building circuits for assignments

lhs : AssignmentLHST
ioAndWireToCompMap : Map<string, Component>
Returns: Map<string, Component>

isCircuitValid circuit varToCompMap

Full Usage: isCircuitValid circuit varToCompMap

Parameters:
Returns: bool

debug:

circuit : Circuit
varToCompMap : Map<string, Component>
Returns: bool

isCircuitValid' comps conns

Full Usage: isCircuitValid' comps conns

Parameters:
Returns: bool

debug:

comps : Component list
conns : Connection list
Returns: bool

joinCircuits inCircuits inPorts topCircuit

Full Usage: joinCircuits inCircuits inPorts topCircuit

Parameters:
Returns: Circuit

Join input ports of topCircuit with inCircuits

inCircuits : Circuit list
inPorts : Port list
topCircuit : Circuit
Returns: Circuit

joinWithMerge lst

Full Usage: joinWithMerge lst

Parameters:
Returns: Circuit * string * Slice * LHSType

Join a list of circuits with MergeWires components

lst : (Circuit * string * Slice * LHSType) list
Returns: Circuit * string * Slice * LHSType

joinWithMerge' circuits

Full Usage: joinWithMerge' circuits

Parameters:
Returns: Circuit
circuits : Circuit list
Returns: Circuit

mainExpressionCircuitBuilder expr ioAndWireToCompMap varSizeMap target

Full Usage: mainExpressionCircuitBuilder expr ioAndWireToCompMap varSizeMap target

Parameters:
Returns: Circuit

The main circuit creation function called with the RHS of an assignment as a parameter Contains 6 recursive functions which eventually build the whole RHS expression The starting point is the buildExpressionCircuit rec function target is 0 if there is no lhs

expr : ExpressionT
ioAndWireToCompMap : Map<string, Component>
varSizeMap : Map<string, int>
target : int
Returns: Circuit

merge2Circuits c1 c2

Full Usage: merge2Circuits c1 c2

Parameters:
Returns: Circuit
c1 : Circuit
c2 : Circuit
Returns: Circuit

mergeIfElse lst1 lst2 varToCompMap

Full Usage: mergeIfElse lst1 lst2 varToCompMap

Parameters:
Returns: List<Option<BitMapping> * Option<BitMapping>>
lst1 : List<BitMapping>
lst2 : List<BitMapping>
varToCompMap : 'a
Returns: List<Option<BitMapping> * Option<BitMapping>>

multiplexerCircuit inputs condition defaultInput

Full Usage: multiplexerCircuit inputs condition defaultInput

Parameters:
Returns: Circuit
inputs : List<bigint * Circuit>
condition : Circuit
defaultInput : Circuit
Returns: Circuit

multiplexerNto1Circuit inputs sel

Full Usage: multiplexerNto1Circuit inputs sel

Parameters:
Returns: Circuit

takes in n - number of inputs, must be a power of 2 circuit being returned has N (bus) data inputs and 1 select

inputs : List<Circuit>
sel : Circuit
Returns: Circuit

overlaps slice1 slice2

Full Usage: overlaps slice1 slice2

Parameters:
Returns: bool
slice1 : Slice
slice2 : Slice
Returns: bool

sliceCircuit circuit width lsb

Full Usage: sliceCircuit circuit width lsb

Parameters:
    circuit : Circuit
    width : int
    lsb : int

Returns: Circuit
circuit : Circuit
width : int
lsb : int
Returns: Circuit

sliceFromBits lhs ioAndWireToCompMap varSizeMap

Full Usage: sliceFromBits lhs ioAndWireToCompMap varSizeMap

Parameters:
Returns: Slice

Extract MSB,LSB from assignment and return as a Slice type Slice = {MSB:int, LSB:int}

lhs : AssignmentLHST
ioAndWireToCompMap : Map<string, Component>
varSizeMap : Map<string, int>
Returns: Slice

sliceFromBitsPrimary primary ioAndWireToCompMap varSizeMap

Full Usage: sliceFromBitsPrimary primary ioAndWireToCompMap varSizeMap

Parameters:
Returns: Slice
primary : PrimaryT
ioAndWireToCompMap : Map<string, Component>
varSizeMap : Map<string, int>
Returns: Slice

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