The design to send to the .NET sidecar: THE sheets this simulation was built from. **Built from the simulation and not from the project, and that is the point.** The renderer has already turned the project into the circuit it simulates - array components expanded into a wrapper and a body - and this hands the sidecar that, so the two processes simulate the same sheets rather than each deriving them from the same input and hoping to agree. They had to agree exactly, because SimSetInputs names a component by ID across the wire and expansion MINTS ids for everything it makes. Two expansions agreeing was luck: the same code over the same list in the same order. Nothing enforced it and nothing tested it. Now only one of the two ever expands, so there is nothing to agree about. It is also why the wire format knows nothing about array components, and must not learn: a SimpleSheet that crossed this boundary is an ordinary sheet by construction.

A simulation carrier with no simulation in it: what the renderer holds when the .NET sidecar is the one simulating. It carries the DESIGN - which answers every structure question the UI asks - the top sheet's IOs, whether the circuit is clocked, and the checked graph, exactly as a real build would. What it does not hold is the expansion: no components, no step arrays, no drivers. Widths and data come from the sidecar - widths through the port slices, data through the reads - and the local fields every gate consults say so: NumStepArrays 0, empty maps. The design is still validated here, by the same checks a build runs, so a design that cannot simulate is refused synchronously with the same error the user has always seen - components highlighted and all. What is skipped is everything after validation: the flatten, the arrays, the ordering.

gets the status of the simulation given current canvasState and project

The currently active FastSimulation - a dummy if none has been built. Callers on wave-sim paths must be guarded by the MODEL saying a wave simulation is live (WaveSimSheet, ws.State): under mutual exclusion the slot then holds that simulation and nothing else can.

look up a sheet in a set of loaded components, return [] or a list of the matching LoadedComponent

look up a sheet in a set of loaded components

canvasState: extracted canvasState from draw block. projLdcs: ldcs from project (current sheet ldc may be outofdate) diagramName: name of current open sheet. return updated list of all LDCs

Helper used convert port into SheetPort for use by wave simulator determining connectivity within a design sheet. name is the name of the containing sheet.

Start up a simulation, doing all necessary checks and generating simulation errors if necesary. The code to do this is quite long so results are memoized. `localBuild` false builds the design-only carrier above instead of a real simulation - what the renderer wants when the sidecar simulates. Truth tables always pass true: they read their own local simulation whatever mode the simulators are in.

canvasState: extracted canvasState from draw block. loadedComponents: from project diagramName: name of current open sheet. save all needed by simulation ldcs in the FastSimulation record. The top sheet name must be saved separately - since if a simulation is being refreshed it must not change

Sheets needed to simulate sheet with name sheet. Sheets form a dependency tree. ldcs is a list of loaded components which must include sheet

THE simulation, memoised against the design it was built from - the single-entry memo that makes "the simulation is a memoised version of the simulation spec" literally true. ONE slot, because Issie runs one simulation at a time: the step and waveform simulators are mutually exclusive, one must be stopped before the other starts, and the only difference between their builds is the array-size parameter - the step simulator wraps a small circular buffer, the waveform simulator sizes the same buffer to hold the whole run so it never wraps. There used to be a slot for each, justified by nothing: the memo can never be warm across a switch, since the array size differs and forces the rebuild anyway. What the second slot did do is let a stopped simulation linger unreleased while the other kind ran - the retention problem the refs harness command exists to chase - and starting either kind now evicts whatever was here by replacing it.

A simulation with everything a wave viewer in this process needs, which is what almost every caller wants. The sidecar is the exception and asks for NoWaveTables.

Extract circuit data from inputs and return a checked SimulationData object or an error SimulationData has some technical debt, it wraps FastSimulation adding some redundant data `waveTables` says whether to build what only a wave viewer reads - see WaveTables.

Extract circuit data from inputs and return a valid SimulationGraph or an error

Does one sheet of a design build into a simulation? The question behind the Simulation tab's verdict button and the wave viewer's price, and the cheapest way to ask it: the graph is checked and thrown away, with no step arrays allocated. **THE one place that says how a design is checked**, and it is written down because it was written twice and the two drifted. The whole design goes to validateCircuitSimulation - the named sheet included - while getStateAndDependencies is asked only for that sheet's canvas: it removes the sheet from the list it returns, and what a sheet IS rather than what is drawn on it (its parameters, and whether it is an ARRAY COMPONENT whose hardware is several copies of what is drawn on it) is on the sheet and not on the canvas. Passing the shortened list on left nothing able to say the sheet being checked was an array component, so the checks ran on its unexpanded canvas and refused its own IO as being on a sheet that is not an array component. `ldcs` is the design as the model holds it now - ModelHelpers.designOf, which puts the canvas being drawn in place of the open sheet's saved copy.