get the module definitions (one per RAM instance) that define RAMs used TODO: make output more compact by using multiple instances of one module where possible. NB. Initial statement is used to initialise RAM as per simulation: should work with Quartus. NB - there is some inconsistency between this definition and current simulation, which will output ram[0] contents in clock 0 on q. the simulation is incompatible with FPGA tools and should change so that initial ram output is always 0.

what verilog declaration should the output signal have?

make a simple testbench which displays module outputs for the first 30 clock cycles

generate an instance of a module named block

get all the RAM and ROM modules used NB at the moment each instance is made a separately named module, for simplicity

get the verilog statements output from each component

return the header of the main verilog module with hardware inputs and outputs in header.

return the wire and reg definitions needed to make the verilog design work.

Get string corresponding to name of signal that drives component input port

get output port name

Get string corresponding to output port name with its width prepended as a Verilog slice. All output ports are internal wire or reg definitions.

Outputs a string which contains a single verilog file with the hardware in verilog form. The top-level simulation moudle is called main - other modules may be included for RAM & ROM this can be called any time after after buildFastSimulation has created the initial FastSimulation data structure. To simulate this you would need to set up clk as a clock input, and provide stimulus for other inputs if there are any.

implement binary operator for two-input gate

Translates from a component to its Verilog description

implement binary operator for multi-input gate

Create fixed width verilog zero. NB it seems this is not strictly needed, integer 0 works!

get valid Verilog constant for bus of given width (may be 1)

take FullName and convert it into a verilog compatible form this is not 1-1, so outputs may not be unique, that is OK

simple way to assign to each component and component output a unique verilog compatible name. outputs will become reg or wire signals in the Verilog