what verilog declaration should the output signal have?

make a simple testbench which displays module outputs for the first 30 clock cycles

get all the RAM and ROM modules used NB at the moment each instance is made a separately named module, for simplicity

get the verilog statements output from each component NB a hybrid component (AsyncRAM1) is in both FClockedComps and FOrderedComps, since it has both clocked and combinational behaviour. Its Verilog describes the whole component, so it must be written once: activeComps drops the hybrid copy from the combinational half.

return the header of the main verilog module with hardware inputs and outputs in header.

return the wire and reg definitions needed to make the verilog design work.

Get string corresponding to name of signal that drives component input port

get output port name

Get string corresponding to output port name with its width prepended as a Verilog slice. All output ports are internal wire or reg definitions.

Outputs a string which contains a single verilog file with the hardware in verilog form. The top-level simulation moudle is called main - other modules may be included for RAM & ROM this can be called any time after after buildFastSimulation has created the initial FastSimulation data structure. To simulate this you would need to set up clk as a clock input, and provide stimulus for other inputs if there are any.

Translates from a component to its Verilog description

The bitwise operator a gate combines its inputs with, before any inversion. Gate inputs are always one bit wide, so the bitwise operators are the right ones.

Implement an n-input gate. The inputs are combined with the un-negated operator and the result inverted once, which is what an n-input NAND/NOR/XNOR gate means, and what getNInpBinaryGateReducer in EvalReference does. Folding the negated operator pairwise instead would give different logic for n > 2.

Create fixed width verilog zero. NB it seems this is not strictly needed, integer 0 works!

get valid Verilog constant for bus of given width (may be 1) NB the digits must be hex, since they follow a 'h prefix: %A or %d would print the value in decimal and Verilog would then read those digits as hex, giving a different (and too wide) number. printf "%x" does not work on bigints, hence hexBignum.

Name of the single instance of that module. Derived from the component name, which writeVerilogNames has already made unique, so instances cannot collide either.

Name of the module generated for a memory component. Distinct from the component's own name, which is already in use as the net driven by the instance: a module and a net sharing an identifier is legal in some tools and rejected by others.

take FullName and convert it into a verilog compatible form this is not 1-1, so outputs may not be unique, that is OK

simple way to assign to each component and component output a unique verilog compatible name. outputs will become reg or wire signals in the Verilog